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[X86][SchedModel] SSE reciprocal square root instruction latencies.
The SSE rsqrt instruction (a fast reciprocal square root estimate) was grouped in the same scheduling IIC_SSE_SQRT* class as the accurate (but very slow) SSE sqrt instruction. For code which uses rsqrt (possibly with newton-raphson iterations) this poor scheduling was affecting performances. This patch splits off the rsqrt instruction from the sqrt instruction scheduling classes and creates new IIC_SSE_RSQER* classes with latency values based on Agner's table. Differential Revision: http://reviews.llvm.org/D5370 Patch by Simon Pilgrim. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218517 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3344,6 +3344,16 @@ def SSE_SQRTSD : OpndItins<
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>;
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>;
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}
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}
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let Sched = WriteFRsqrt in {
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def SSE_RSQRTPS : OpndItins<
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IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
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>;
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def SSE_RSQRTSS : OpndItins<
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IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
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>;
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}
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let Sched = WriteFRcp in {
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let Sched = WriteFRcp in {
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def SSE_RCPP : OpndItins<
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def SSE_RCPP : OpndItins<
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IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
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IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
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@ -3622,10 +3632,10 @@ defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
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// Reciprocal approximations. Note that these typically require refinement
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// Reciprocal approximations. Note that these typically require refinement
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// in order to obtain suitable precision.
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// in order to obtain suitable precision.
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defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTSS>,
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defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
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sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTPS>,
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sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>,
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sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
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sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
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int_x86_avx_rsqrt_ps_256, SSE_SQRTPS>;
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int_x86_avx_rsqrt_ps_256, SSE_RSQRTPS>;
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defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
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defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
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sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
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sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
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sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
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sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
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@ -129,6 +129,7 @@ defm : HWWriteResPair<WriteFAdd, HWPort1, 3>;
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defm : HWWriteResPair<WriteFMul, HWPort0, 5>;
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defm : HWWriteResPair<WriteFMul, HWPort0, 5>;
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defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles.
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defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles.
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defm : HWWriteResPair<WriteFRcp, HWPort0, 5>;
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defm : HWWriteResPair<WriteFRcp, HWPort0, 5>;
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defm : HWWriteResPair<WriteFRsqrt, HWPort0, 5>;
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defm : HWWriteResPair<WriteFSqrt, HWPort0, 15>;
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defm : HWWriteResPair<WriteFSqrt, HWPort0, 15>;
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defm : HWWriteResPair<WriteCvtF2I, HWPort1, 3>;
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defm : HWWriteResPair<WriteCvtF2I, HWPort1, 3>;
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defm : HWWriteResPair<WriteCvtI2F, HWPort1, 4>;
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defm : HWWriteResPair<WriteCvtI2F, HWPort1, 4>;
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@ -117,6 +117,7 @@ defm : SBWriteResPair<WriteFAdd, SBPort1, 3>;
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defm : SBWriteResPair<WriteFMul, SBPort0, 5>;
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defm : SBWriteResPair<WriteFMul, SBPort0, 5>;
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defm : SBWriteResPair<WriteFDiv, SBPort0, 12>; // 10-14 cycles.
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defm : SBWriteResPair<WriteFDiv, SBPort0, 12>; // 10-14 cycles.
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defm : SBWriteResPair<WriteFRcp, SBPort0, 5>;
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defm : SBWriteResPair<WriteFRcp, SBPort0, 5>;
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defm : SBWriteResPair<WriteFRsqrt, SBPort0, 5>;
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defm : SBWriteResPair<WriteFSqrt, SBPort0, 15>;
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defm : SBWriteResPair<WriteFSqrt, SBPort0, 15>;
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defm : SBWriteResPair<WriteCvtF2I, SBPort1, 3>;
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defm : SBWriteResPair<WriteCvtF2I, SBPort1, 3>;
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defm : SBWriteResPair<WriteCvtI2F, SBPort1, 4>;
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defm : SBWriteResPair<WriteCvtI2F, SBPort1, 4>;
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@ -67,7 +67,8 @@ defm WriteFAdd : X86SchedWritePair; // Floating point add/sub/compare.
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defm WriteFMul : X86SchedWritePair; // Floating point multiplication.
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defm WriteFMul : X86SchedWritePair; // Floating point multiplication.
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defm WriteFDiv : X86SchedWritePair; // Floating point division.
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defm WriteFDiv : X86SchedWritePair; // Floating point division.
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defm WriteFSqrt : X86SchedWritePair; // Floating point square root.
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defm WriteFSqrt : X86SchedWritePair; // Floating point square root.
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defm WriteFRcp : X86SchedWritePair; // Floating point reciprocal.
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defm WriteFRcp : X86SchedWritePair; // Floating point reciprocal estimate.
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defm WriteFRsqrt : X86SchedWritePair; // Floating point reciprocal square root estimate.
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defm WriteFMA : X86SchedWritePair; // Fused Multiply Add.
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defm WriteFMA : X86SchedWritePair; // Fused Multiply Add.
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defm WriteFShuffle : X86SchedWritePair; // Floating point vector shuffles.
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defm WriteFShuffle : X86SchedWritePair; // Floating point vector shuffles.
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defm WriteFBlend : X86SchedWritePair; // Floating point vector blends.
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defm WriteFBlend : X86SchedWritePair; // Floating point vector blends.
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@ -314,6 +315,11 @@ def IIC_SSE_SQRTPD_RM : InstrItinClass;
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def IIC_SSE_SQRTSD_RR : InstrItinClass;
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def IIC_SSE_SQRTSD_RR : InstrItinClass;
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def IIC_SSE_SQRTSD_RM : InstrItinClass;
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def IIC_SSE_SQRTSD_RM : InstrItinClass;
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def IIC_SSE_RSQRTPS_RR : InstrItinClass;
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def IIC_SSE_RSQRTPS_RM : InstrItinClass;
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def IIC_SSE_RSQRTSS_RR : InstrItinClass;
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def IIC_SSE_RSQRTSS_RM : InstrItinClass;
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def IIC_SSE_RCPP_RR : InstrItinClass;
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def IIC_SSE_RCPP_RR : InstrItinClass;
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def IIC_SSE_RCPP_RM : InstrItinClass;
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def IIC_SSE_RCPP_RM : InstrItinClass;
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def IIC_SSE_RCPS_RR : InstrItinClass;
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def IIC_SSE_RCPS_RR : InstrItinClass;
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@ -224,6 +224,11 @@ def AtomItineraries : ProcessorItineraries<
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InstrItinData<IIC_SSE_SQRTSD_RR, [InstrStage<62, [Port0, Port1]>] >,
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InstrItinData<IIC_SSE_SQRTSD_RR, [InstrStage<62, [Port0, Port1]>] >,
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InstrItinData<IIC_SSE_SQRTSD_RM, [InstrStage<62, [Port0, Port1]>] >,
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InstrItinData<IIC_SSE_SQRTSD_RM, [InstrStage<62, [Port0, Port1]>] >,
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InstrItinData<IIC_SSE_RSQRTPS_RR, [InstrStage<9, [Port0, Port1]>] >,
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InstrItinData<IIC_SSE_RSQRTPS_RM, [InstrStage<10, [Port0, Port1]>] >,
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InstrItinData<IIC_SSE_RSQRTSS_RR, [InstrStage<4, [Port0]>] >,
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InstrItinData<IIC_SSE_RSQRTSS_RM, [InstrStage<4, [Port0]>] >,
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InstrItinData<IIC_SSE_RCPP_RR, [InstrStage<9, [Port0, Port1]>] >,
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InstrItinData<IIC_SSE_RCPP_RR, [InstrStage<9, [Port0, Port1]>] >,
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InstrItinData<IIC_SSE_RCPP_RM, [InstrStage<10, [Port0, Port1]>] >,
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InstrItinData<IIC_SSE_RCPP_RM, [InstrStage<10, [Port0, Port1]>] >,
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InstrItinData<IIC_SSE_RCPS_RR, [InstrStage<4, [Port0]>] >,
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InstrItinData<IIC_SSE_RCPS_RR, [InstrStage<4, [Port0]>] >,
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@ -163,13 +163,13 @@ defm : JWriteResIntPair<WriteJump, JALU01, 1>;
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// FIXME: should we bother splitting JFPU pipe + unit stages for fast instructions?
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// FIXME: should we bother splitting JFPU pipe + unit stages for fast instructions?
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// FIXME: Double precision latencies
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// FIXME: Double precision latencies
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// FIXME: SS vs PS latencies
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// FIXME: SS vs PS latencies
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// FIXME: RSQRT latencies
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// FIXME: ymm latencies
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// FIXME: ymm latencies
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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defm : JWriteResFpuPair<WriteFAdd, JFPU0, 3>;
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defm : JWriteResFpuPair<WriteFAdd, JFPU0, 3>;
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defm : JWriteResFpuPair<WriteFMul, JFPU1, 2>;
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defm : JWriteResFpuPair<WriteFMul, JFPU1, 2>;
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defm : JWriteResFpuPair<WriteFRcp, JFPU1, 2>;
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defm : JWriteResFpuPair<WriteFRcp, JFPU1, 2>;
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defm : JWriteResFpuPair<WriteFRsqrt, JFPU1, 2>;
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defm : JWriteResFpuPair<WriteFShuffle, JFPU01, 1>;
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defm : JWriteResFpuPair<WriteFShuffle, JFPU01, 1>;
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defm : JWriteResFpuPair<WriteFBlend, JFPU01, 1>;
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defm : JWriteResFpuPair<WriteFBlend, JFPU01, 1>;
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defm : JWriteResFpuPair<WriteFShuffle256, JFPU01, 1>;
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defm : JWriteResFpuPair<WriteFShuffle256, JFPU01, 1>;
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@ -101,6 +101,7 @@ def : WriteRes<WriteIDivLd, [MEC_RSV, IEC_RSV01, SMDivider]> {
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// Scalar and vector floating point.
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// Scalar and vector floating point.
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defm : SMWriteResPair<WriteFAdd, FPC_RSV1, 3>;
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defm : SMWriteResPair<WriteFAdd, FPC_RSV1, 3>;
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defm : SMWriteResPair<WriteFRcp, FPC_RSV0, 5>;
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defm : SMWriteResPair<WriteFRcp, FPC_RSV0, 5>;
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defm : SMWriteResPair<WriteFRsqrt, FPC_RSV0, 5>;
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defm : SMWriteResPair<WriteFSqrt, FPC_RSV0, 15>;
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defm : SMWriteResPair<WriteFSqrt, FPC_RSV0, 15>;
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defm : SMWriteResPair<WriteCvtF2I, FPC_RSV01, 4>;
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defm : SMWriteResPair<WriteCvtF2I, FPC_RSV01, 4>;
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defm : SMWriteResPair<WriteCvtI2F, FPC_RSV01, 4>;
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defm : SMWriteResPair<WriteCvtI2F, FPC_RSV01, 4>;
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