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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
Rework arm fast isel branch and compare code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114226 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -694,7 +694,54 @@ bool ARMFastISel::ARMSelectStore(const Instruction *I) {
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if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false;
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return false;
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return true;
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}
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static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
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switch (Pred) {
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// Needs two compares...
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case CmpInst::FCMP_ONE:
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case CmpInst::FCMP_UEQ:
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default:
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assert(false && "Unhandled CmpInst::Predicate!");
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return ARMCC::AL;
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case CmpInst::ICMP_EQ:
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case CmpInst::FCMP_OEQ:
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return ARMCC::EQ;
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case CmpInst::ICMP_SGT:
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case CmpInst::FCMP_OGT:
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return ARMCC::GT;
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case CmpInst::ICMP_SGE:
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case CmpInst::FCMP_OGE:
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return ARMCC::GE;
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case CmpInst::ICMP_UGT:
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case CmpInst::FCMP_UGT:
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return ARMCC::HI;
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case CmpInst::FCMP_OLT:
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return ARMCC::MI;
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case CmpInst::ICMP_ULE:
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case CmpInst::FCMP_OLE:
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return ARMCC::LS;
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case CmpInst::FCMP_ORD:
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return ARMCC::VC;
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case CmpInst::FCMP_UNO:
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return ARMCC::VS;
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case CmpInst::FCMP_UGE:
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return ARMCC::PL;
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case CmpInst::ICMP_SLT:
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case CmpInst::FCMP_ULT:
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return ARMCC::LT;
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case CmpInst::ICMP_SLE:
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case CmpInst::FCMP_ULE:
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return ARMCC::LE;
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case CmpInst::FCMP_UNE:
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case CmpInst::ICMP_NE:
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return ARMCC::NE;
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case CmpInst::ICMP_UGE:
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return ARMCC::HS;
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case CmpInst::ICMP_ULT:
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return ARMCC::LO;
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}
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}
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bool ARMFastISel::ARMSelectBranch(const Instruction *I) {
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@ -703,18 +750,28 @@ bool ARMFastISel::ARMSelectBranch(const Instruction *I) {
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MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
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// Simple branch support.
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unsigned CondReg = getRegForValue(BI->getCondition());
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// TODO: Hopefully we've already handled the condition since we won't
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// have left an update in the value map. See the TODO below in ARMSelectCMP.
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Value *Cond = BI->getCondition();
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unsigned CondReg = getRegForValue(Cond);
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if (CondReg == 0) return false;
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unsigned CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
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ARMCC::CondCodes ARMPred = ARMCC::NE;
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CmpInst *CI = dyn_cast<CmpInst>(Cond);
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if (!CI) return false;
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// Get the compare predicate.
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ARMPred = getComparePred(CI->getPredicate());
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// We may not handle every CC for now.
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if (ARMPred == ARMCC::AL) return false;
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unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
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.addReg(CondReg).addReg(CondReg));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
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.addMBB(TBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
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.addMBB(TBB).addImm(ARMPred).addReg(CondReg);
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FastEmitBranch(FBB, DL);
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FuncInfo.MBB->addSuccessor(TBB);
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return true;
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return true;
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}
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bool ARMFastISel::ARMSelectCmp(const Instruction *I) {
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@ -730,17 +787,21 @@ bool ARMFastISel::ARMSelectCmp(const Instruction *I) {
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return false;
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unsigned CmpOpc;
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unsigned DestReg;
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switch (VT.getSimpleVT().SimpleTy) {
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default: return false;
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// TODO: Verify compares.
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case MVT::f32:
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CmpOpc = ARM::VCMPES;
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DestReg = ARM::FPSCR;
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break;
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case MVT::f64:
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CmpOpc = ARM::VCMPED;
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DestReg = ARM::FPSCR;
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break;
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case MVT::i32:
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CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
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DestReg = ARM::CPSR;
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break;
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}
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@ -759,7 +820,8 @@ bool ARMFastISel::ARMSelectCmp(const Instruction *I) {
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::FMSTAT)));
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// TODO: How to update the value map when there's no result reg?
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// Update the value to the implicit def reg.
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UpdateValueMap(I, DestReg);
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return true;
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}
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