6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-17 18:24:34 +00:00
Code Issues Projects Releases Wiki Activity

MIR Serialization: Serialize the machine function's liveins.

Browse Source 
Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243288 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alex Lorenz
2015-07-27 17:42:45 +00:00
parent b7abbca1dd
commit a5da4f1f8d
8 changed files with 165 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
lib/CodeGen/MIRParser/MIParser.cpp
View File

@@ -98,6 +98,7 @@ public:
bool parse(MachineInstr *&MI);
bool parseMBB(MachineBasicBlock *&MBB);
bool parseNamedRegister(unsigned &Reg);
bool parseStandaloneVirtualRegister(unsigned &Reg);
bool parseRegister(unsigned &Reg);
bool parseRegisterFlag(unsigned &Flags);
@@ -289,6 +290,18 @@ bool MIParser::parseNamedRegister(unsigned &Reg) {
return false;
}
bool MIParser::parseStandaloneVirtualRegister(unsigned &Reg) {
lex();
if (Token.isNot(MIToken::VirtualRegister))
return error("expected a virtual register");
if (parseRegister(Reg))
return 0;
lex();
if (Token.isNot(MIToken::Eof))
return error("expected end of string after the register reference");
return false;
}
static const char *printImplicitRegisterFlag(const MachineOperand &MO) {
assert(MO.isImplicit());
return MO.isDef() ? "implicit-def" : "implicit";
@@ -843,3 +856,12 @@ bool llvm::parseNamedRegisterReference(unsigned &Reg, SourceMgr &SM,
SMDiagnostic &Error) {
return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseNamedRegister(Reg);
}
bool llvm::parseVirtualRegisterReference(unsigned &Reg, SourceMgr &SM,
MachineFunction &MF, StringRef Src,
const PerFunctionMIParsingState &PFS,
const SlotMapping &IRSlots,
SMDiagnostic &Error) {
return MIParser(SM, MF, Error, Src, PFS, IRSlots)
.parseStandaloneVirtualRegister(Reg);
}