6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-02 19:24:25 +00:00
Code Issues Projects Releases Wiki Activity

Start TargetRegisterClass indices at 0 instead of 1, so that

Browse Source 
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2010-06-18 18:13:55 +00:00
parent df50d7e238
commit a606d955de
9 changed files with 56 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/Target/TargetInstrDesc.h
View File

@ -55,7 +55,7 @@ public:
///
/// NOTE: This member should be considered to be private, all access should go
/// through "getRegClass(TRI)" below.
unsigned short RegClass;
short RegClass;
/// Flags - These are flags from the TOI::OperandFlags enum.
unsigned short Flags;

4
include/llvm/Target/TargetRegisterInfo.h
View File

@ -523,8 +523,8 @@ public:
/// getRegClass - Returns the register class associated with the enumeration
/// value. See class TargetOperandInfo.
const TargetRegisterClass *getRegClass(unsigned i) const {
assert(i <= getNumRegClasses() && "Register Class ID out of range");
return i ? RegClassBegin[i - 1] : NULL;
assert(i < getNumRegClasses() && "Register Class ID out of range");
return RegClassBegin[i];
}
/// getPointerRegClass - Returns a TargetRegisterClass used for pointer