From a623f5a58dd7768b0cf4dbb61b1fffa8b4d07cca Mon Sep 17 00:00:00 2001
From: Jim Grosbach <grosbach@apple.com>
Date: Mon, 14 Dec 2009 19:24:11 +0000
Subject: [PATCH] correct selection requirements for thumb2 vs. arm versions of
 the barrier intrinsics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91313 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMInstrInfo.td   | 4 ++--
 lib/Target/ARM/ARMInstrThumb2.td | 6 ++++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 814f50656f5..8f947febb61 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1579,7 +1579,7 @@ def Int_MemBarrierV7 : AInoP<(outs), (ins),
                         Pseudo, NoItinerary,
                         "dmb", "",
                         [(ARMMemBarrier)]>,
-                        Requires<[HasV7]> {
+                        Requires<[IsARM, HasV7]> {
   let Inst{31-4} = 0xf57ff05;
   // FIXME: add support for options other than a full system DMB
   let Inst{3-0} = 0b1111;
@@ -1589,7 +1589,7 @@ def Int_SyncBarrierV7 : AInoP<(outs), (ins),
                         Pseudo, NoItinerary,
                         "dsb", "",
                         [(ARMSyncBarrier)]>,
-                        Requires<[HasV7]> {
+                        Requires<[IsARM, HasV7]> {
   let Inst{31-4} = 0xf57ff04;
   // FIXME: add support for options other than a full system DSB
   let Inst{3-0} = 0b1111;
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 0f2024f4fa8..a2aa1c03e93 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -1073,14 +1073,16 @@ let hasSideEffects = 1 in {
 def t2Int_MemBarrierV7 : AInoP<(outs), (ins),
                         Pseudo, NoItinerary,
                         "dmb", "",
-                        [(ARMMemBarrier)]> {
+                        [(ARMMemBarrier)]>,
+                        Requires<[IsThumb2]> {
   // FIXME: add support for options other than a full system DMB
 }
 
 def t2Int_SyncBarrierV7 : AInoP<(outs), (ins),
                         Pseudo, NoItinerary,
                         "dsb", "",
-                        [(ARMSyncBarrier)]> {
+                        [(ARMSyncBarrier)]>,
+                        Requires<[IsThumb2]> {
   // FIXME: add support for options other than a full system DSB
 }
 }