mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Checking in code that works on my simple test case. However, there is still a bug with branches that I need to fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16979 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tanya Lattner
parent
a671f3b1d4
commit
a645750722
@ -1192,16 +1192,14 @@ void ModuloSchedulingPass::writePrologues(std::vector<MachineBasicBlock *> &prol
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int maxStageCount = 0;
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MSchedGraphNode *branch = 0;
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MSchedGraphNode *BAbranch = 0;
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for(MSSchedule::kernel_iterator I = schedule.kernel_begin(), E = schedule.kernel_end(); I != E; ++I) {
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maxStageCount = std::max(maxStageCount, I->second);
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//Ignore the branch, we will handle this separately
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if(I->first->isBranch()) {
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if (I->first->getInst()->getOpcode() == V9::BA)
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BAbranch = I->first;
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else
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if (I->first->getInst()->getOpcode() != V9::BA)
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branch = I->first;
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continue;
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}
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@ -1241,6 +1239,10 @@ void ModuloSchedulingPass::writePrologues(std::vector<MachineBasicBlock *> &prol
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//Save copy in tmpInstruction
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tmp = new TmpInstruction(mOp.getVRegValue());
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//Get machine code for this instruction
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MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get((Instruction*) mOp.getVRegValue());
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tempMvec.addTemp((Value*) tmp);
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DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue()) << " New Value: " << *tmp << " Stage: " << i << "\n");
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newValues[mOp.getVRegValue()][i]= tmp;
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@ -1275,8 +1277,6 @@ void ModuloSchedulingPass::writePrologues(std::vector<MachineBasicBlock *> &prol
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//Stick in branch at the end
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machineBB->push_back(branch->getInst()->clone());
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//Stick in BA branch at the end
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machineBB->push_back(BAbranch->getInst()->clone());
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(((MachineBasicBlock*)origBB)->getParent())->getBasicBlockList().push_back(machineBB);
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prologues.push_back(machineBB);
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@ -1322,7 +1322,7 @@ void ModuloSchedulingPass::writeEpilogues(std::vector<MachineBasicBlock *> &epil
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DEBUG(std::cerr << " Epilogue #: " << i << "\n");
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std::map<Value*, int> inEpilogue;
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for(MachineBasicBlock::const_iterator MI = origBB->begin(), ME = origBB->end(); ME != MI; ++MI) {
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for(int j=schedule.getMaxStage(); j > i; --j) {
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@ -1334,19 +1334,25 @@ void ModuloSchedulingPass::writeEpilogues(std::vector<MachineBasicBlock *> &epil
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for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) {
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//get machine operand
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const MachineOperand &mOp = clone->getOperand(opNum);
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//If this is the last instructions for the max iterations ago, don't update operands
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if(j == schedule.getMaxStage() && (i == 0))
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continue;
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if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) {
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DEBUG(std::cerr << "Writing PHI for " << *(mOp.getVRegValue()) << "\n");
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//If this is the last instructions for the max iterations ago, don't update operands
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if(inEpilogue.count(mOp.getVRegValue()))
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if(inEpilogue[mOp.getVRegValue()] == i)
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continue;
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//Quickly write appropriate phis for this operand
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if(newValues.count(mOp.getVRegValue())) {
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if(newValues[mOp.getVRegValue()].count(i)) {
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Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]);
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//Get machine code for this instruction
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MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get((Instruction*) mOp.getVRegValue());
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tempMvec.addTemp((Value*) tmp);
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MachineInstr *saveValue = BuildMI(machineBB, V9::PHI, 3).addReg(newValues[mOp.getVRegValue()][i]).addReg(kernelPHIs[mOp.getVRegValue()][i]).addRegDef(tmp);
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DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
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valPHIs[mOp.getVRegValue()] = tmp;
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@ -1358,6 +1364,9 @@ void ModuloSchedulingPass::writeEpilogues(std::vector<MachineBasicBlock *> &epil
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clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]);
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}
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}
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else if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef())) {
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inEpilogue[mOp.getVRegValue()] = i;
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}
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}
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machineBB->push_back(clone);
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}
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@ -1392,6 +1401,10 @@ void ModuloSchedulingPass::writeKernel(BasicBlock *llvmBB, MachineBasicBlock *ma
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//Insert into machine basic block
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machineBB->push_back(instClone);
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if(I->first->isBranch()) {
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//Add kernel noop
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BuildMI(machineBB, V9::NOP, 0);
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}
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//Loop over Machine Operands
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for(unsigned i=0; i < inst->getNumOperands(); ++i) {
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@ -1409,6 +1422,10 @@ void ModuloSchedulingPass::writeKernel(BasicBlock *llvmBB, MachineBasicBlock *ma
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//If its in the value saved, we need to create a temp instruction and use that instead
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if(valuesToSave.count(mOp.getVRegValue())) {
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TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
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//Get machine code for this instruction
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MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get((Instruction*) mOp.getVRegValue());
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tempMvec.addTemp((Value*) tmp);
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//Update the operand in the cloned instruction
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instClone->getOperand(i).setValueReg(tmp);
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@ -1425,6 +1442,10 @@ void ModuloSchedulingPass::writeKernel(BasicBlock *llvmBB, MachineBasicBlock *ma
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TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
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//Get machine code for this instruction
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MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get((Instruction*) mOp.getVRegValue());
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tempVec.addTemp((Value*) tmp);
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//Create new machine instr and put in MBB
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MachineInstr *saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
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@ -1476,12 +1497,23 @@ void ModuloSchedulingPass::writeKernel(BasicBlock *llvmBB, MachineBasicBlock *ma
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if(count < (V->second).size()) {
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if(lastPhi == 0) {
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lastPhi = new TmpInstruction(I->second);
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//Get machine code for this instruction
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MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get((Instruction*) V->first);
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tempMvec.addTemp((Value*) lastPhi);
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MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(kernelValue[V->first]).addReg(I->second).addRegDef(lastPhi);
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DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
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newValLocation[lastPhi] = machineBB;
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}
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else {
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Instruction *tmp = new TmpInstruction(I->second);
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//Get machine code for this instruction
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MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get((Instruction*) V->first);
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tempMvec.addTemp((Value*) tmp);
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MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp);
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DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
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lastPhi = tmp;
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@ -1513,60 +1545,97 @@ void ModuloSchedulingPass::removePHIs(const MachineBasicBlock *origBB, std::vect
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//Worklist to delete things
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std::vector<std::pair<MachineBasicBlock*, MachineBasicBlock::iterator> > worklist;
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//Worklist of TmpInstructions that need to be added to a MCFI
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std::vector<Instruction*> addToMCFI;
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//Worklist to add OR instructions to end of kernel so not to invalidate the iterator
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//std::vector<std::pair<Instruction*, Value*> > newORs;
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const TargetInstrInfo *TMI = target.getInstrInfo();
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//Start with the kernel and for each phi insert a copy for the phi def and for each arg
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for(MachineBasicBlock::iterator I = kernelBB->begin(), E = kernelBB->end(); I != E; ++I) {
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//Get op code and check if its a phi
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if(I->getOpcode() == V9::PHI) {
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Instruction *tmp = 0;
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for(unsigned i = 0; i < I->getNumOperands(); ++i) {
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//Get Operand
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const MachineOperand &mOp = I->getOperand(i);
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assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n");
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if(!tmp) {
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tmp = new TmpInstruction(mOp.getVRegValue());
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}
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if(I->getOpcode() == V9::PHI) {
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DEBUG(std::cerr << "Replacing PHI: " << *I << "\n");
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Instruction *tmp = 0;
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//Now for all our arguments we read, OR to the new TmpInstruction that we created
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if(mOp.isUse()) {
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DEBUG(std::cerr << "Use: " << mOp << "\n");
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//Place a copy at the end of its BB but before the branches
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assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
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//Reverse iterate to find the branches, we can safely assume no instructions have been
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//put in the nop positions
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for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
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MachineOpCode opc = inst->getOpcode();
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if(TMI->isBranch(opc) || TMI->isNop(opc))
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continue;
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else {
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BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
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break;
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}
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}
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for(unsigned i = 0; i < I->getNumOperands(); ++i) {
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//Get Operand
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const MachineOperand &mOp = I->getOperand(i);
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assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n");
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if(!tmp) {
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tmp = new TmpInstruction(mOp.getVRegValue());
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addToMCFI.push_back(tmp);
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}
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}
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else {
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//Remove the phi and replace it with an OR
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DEBUG(std::cerr << "Def: " << mOp << "\n");
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BuildMI(*kernelBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
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worklist.push_back(std::make_pair(kernelBB, I));
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}
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//Now for all our arguments we read, OR to the new TmpInstruction that we created
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if(mOp.isUse()) {
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DEBUG(std::cerr << "Use: " << mOp << "\n");
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//Place a copy at the end of its BB but before the branches
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assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
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//Reverse iterate to find the branches, we can safely assume no instructions have been
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//put in the nop positions
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for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
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MachineOpCode opc = inst->getOpcode();
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if(TMI->isBranch(opc) || TMI->isNop(opc))
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continue;
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else {
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BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
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break;
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}
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}
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}
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}
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}
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else {
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//Remove the phi and replace it with an OR
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DEBUG(std::cerr << "Def: " << mOp << "\n");
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//newORs.push_back(std::make_pair(tmp, mOp.getVRegValue()));
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BuildMI(*kernelBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
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worklist.push_back(std::make_pair(kernelBB, I));
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}
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}
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}
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else {
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//We found an instruction that we can add to its mcfi
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if(addToMCFI.size() > 0) {
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for(unsigned i = 0; i < I->getNumOperands(); ++i) {
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const MachineOperand &mOp = I->getOperand(i);
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if(mOp.getType() == MachineOperand::MO_VirtualRegister) {
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if(!isa<TmpInstruction>(mOp.getVRegValue()) && !isa<PHINode>(mOp.getVRegValue())) {
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//Get machine code for this instruction
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MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get((Instruction*) mOp.getVRegValue());
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for(unsigned x = 0; x < addToMCFI.size(); ++x) {
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tempMvec.addTemp(addToMCFI[x]);
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}
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addToMCFI.clear();
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break;
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}
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}
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}
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}
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}
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}
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//for(std::vector<std::pair<Instruction*, Value*> >::reverse_iterator I = newORs.rbegin(), IE = newORs.rend(); I != IE; ++I)
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//BuildMI(*kernelBB, kernelBB->begin(), V9::ORr, 3).addReg(I->first).addImm(0).addRegDef(I->second);
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//Remove phis from epilogue
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for(std::vector<MachineBasicBlock*>::iterator MB = epilogues.begin(), ME = epilogues.end(); MB != ME; ++MB) {
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for(MachineBasicBlock::iterator I = (*MB)->begin(), E = (*MB)->end(); I != E; ++I) {
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//Get op code and check if its a phi
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if(I->getOpcode() == V9::PHI) {
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Instruction *tmp = 0;
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for(unsigned i = 0; i < I->getNumOperands(); ++i) {
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//Get Operand
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const MachineOperand &mOp = I->getOperand(i);
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@ -1574,6 +1643,7 @@ void ModuloSchedulingPass::removePHIs(const MachineBasicBlock *origBB, std::vect
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if(!tmp) {
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tmp = new TmpInstruction(mOp.getVRegValue());
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addToMCFI.push_back(tmp);
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}
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//Now for all our arguments we read, OR to the new TmpInstruction that we created
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@ -1593,7 +1663,7 @@ void ModuloSchedulingPass::removePHIs(const MachineBasicBlock *origBB, std::vect
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}
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}
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}
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else {
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//Remove the phi and replace it with an OR
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@ -1604,16 +1674,40 @@ void ModuloSchedulingPass::removePHIs(const MachineBasicBlock *origBB, std::vect
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}
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}
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else {
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//We found an instruction that we can add to its mcfi
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if(addToMCFI.size() > 0) {
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for(unsigned i = 0; i < I->getNumOperands(); ++i) {
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const MachineOperand &mOp = I->getOperand(i);
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if(mOp.getType() == MachineOperand::MO_VirtualRegister) {
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if(!isa<TmpInstruction>(mOp.getVRegValue()) && !isa<PHINode>(mOp.getVRegValue())) {
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//Get machine code for this instruction
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MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get((Instruction*) mOp.getVRegValue());
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for(unsigned x = 0; x < addToMCFI.size(); ++x) {
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tempMvec.addTemp(addToMCFI[x]);
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}
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addToMCFI.clear();
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break;
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}
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}
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}
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}
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}
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}
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}
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//Delete the phis
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for(std::vector<std::pair<MachineBasicBlock*, MachineBasicBlock::iterator> >::iterator I = worklist.begin(), E = worklist.end(); I != E; ++I) {
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DEBUG(std::cerr << "Deleting PHI " << I->second << "\n");
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DEBUG(std::cerr << "Deleting PHI " << *I->second << "\n");
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I->first->erase(I->second);
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}
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assert((addToMCFI.size() == 0) && "We should have added all TmpInstructions to some MachineCodeForInstruction");
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}
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@ -1744,30 +1838,34 @@ void ModuloSchedulingPass::reconstructLoop(MachineBasicBlock *BB) {
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}
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}
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//Update branch
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for(unsigned opNum = 0; opNum < branch->getNumOperands(); ++opNum) {
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MachineOperand &mOp = branch->getOperand(opNum);
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if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
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mOp.setValueReg(llvm_epilogues[(llvm_epilogues.size()-1-I)]);
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}
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}
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//Update llvm basic block with our new branch instr
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DEBUG(std::cerr << BB->getBasicBlock()->getTerminator() << "\n");
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const BranchInst *branchVal = dyn_cast<BranchInst>(BB->getBasicBlock()->getTerminator());
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TmpInstruction *tmp = new TmpInstruction(branchVal->getCondition());
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//TmpInstruction *tmp = new TmpInstruction(branchVal->getCondition());
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//Add TmpInstruction to original branches MCFI
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//MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(branchVal);
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//tempMvec.addTemp((Value*) tmp);
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if(I == prologues.size()-1) {
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TerminatorInst *newBranch = new BranchInst(llvmKernelBB,
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llvm_epilogues[(llvm_epilogues.size()-1-I)],
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tmp,
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branchVal->getCondition(),
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llvm_prologues[I]);
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}
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else
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TerminatorInst *newBranch = new BranchInst(llvm_prologues[I+1],
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llvm_epilogues[(llvm_epilogues.size()-1-I)],
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tmp,
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branchVal->getCondition(),
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llvm_prologues[I]);
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assert(branch != 0 && "There must be a terminator for this machine basic block!\n");
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@ -1776,8 +1874,9 @@ void ModuloSchedulingPass::reconstructLoop(MachineBasicBlock *BB) {
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BuildMI(prologues[I], V9::NOP, 0);
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//Add a unconditional branch to the next prologue
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if(I != prologues.size()-1)
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if(I != prologues.size()-1) {
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BuildMI(prologues[I], V9::BA, 1).addPCDisp(llvm_prologues[I+1]);
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}
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else
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BuildMI(prologues[I], V9::BA, 1).addPCDisp(llvmKernelBB);
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@ -1787,12 +1886,18 @@ void ModuloSchedulingPass::reconstructLoop(MachineBasicBlock *BB) {
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//Fix up kernel machine branches
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MachineInstr *branch = 0;
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||||
MachineInstr *BAbranch = 0;
|
||||
|
||||
for(MachineBasicBlock::reverse_iterator mInst = machineKernelBB->rbegin(), mInstEnd = machineKernelBB->rend(); mInst != mInstEnd; ++mInst) {
|
||||
MachineOpCode OC = mInst->getOpcode();
|
||||
if(TMI->isBranch(OC)) {
|
||||
branch = &*mInst;
|
||||
DEBUG(std::cerr << *mInst << "\n");
|
||||
break;
|
||||
if(mInst->getOpcode() == V9::BA) {
|
||||
BAbranch = &*mInst;
|
||||
}
|
||||
else {
|
||||
branch = &*mInst;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1807,27 +1912,39 @@ void ModuloSchedulingPass::reconstructLoop(MachineBasicBlock *BB) {
|
||||
}
|
||||
}
|
||||
|
||||
Value *origBAVal = 0;
|
||||
|
||||
//Update kernel BA branch
|
||||
for(unsigned opNum = 0; opNum < BAbranch->getNumOperands(); ++opNum) {
|
||||
MachineOperand &mOp = BAbranch->getOperand(opNum);
|
||||
if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
|
||||
origBAVal = mOp.getVRegValue();
|
||||
if(llvm_epilogues.size() > 0)
|
||||
mOp.setValueReg(llvm_epilogues[0]);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
assert((origBAVal != 0) && "Could not find original branch always value");
|
||||
|
||||
//Update kernelLLVM branches
|
||||
const BranchInst *branchVal = dyn_cast<BranchInst>(BB->getBasicBlock()->getTerminator());
|
||||
//TmpInstruction *tmp = new TmpInstruction(branchVal->getCondition());
|
||||
|
||||
//Add TmpInstruction to original branches MCFI
|
||||
//MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(branchVal);
|
||||
//tempMvec.addTemp((Value*) tmp);
|
||||
|
||||
TerminatorInst *newBranch = new BranchInst(llvmKernelBB,
|
||||
llvm_epilogues[0],
|
||||
new TmpInstruction(branchVal->getCondition()),
|
||||
branchVal->getCondition(),
|
||||
llvmKernelBB);
|
||||
|
||||
//Add kernel noop
|
||||
BuildMI(machineKernelBB, V9::NOP, 0);
|
||||
|
||||
//Add unconditional branch to first epilogue
|
||||
BuildMI(machineKernelBB, V9::BA, 1).addPCDisp(llvm_epilogues[0]);
|
||||
|
||||
|
||||
//Add kernel noop
|
||||
BuildMI(machineKernelBB, V9::NOP, 0);
|
||||
|
||||
//Lastly add unconditional branches for the epilogues
|
||||
for(unsigned I = 0; I < epilogues.size(); ++I) {
|
||||
|
||||
//Now since I don't trust fall throughs, add a unconditional branch to the next prologue
|
||||
//Now since we don't have fall throughs, add a unconditional branch to the next prologue
|
||||
if(I != epilogues.size()-1) {
|
||||
BuildMI(epilogues[I], V9::BA, 1).addPCDisp(llvm_epilogues[I+1]);
|
||||
//Add unconditional branch to end of epilogue
|
||||
@ -1835,41 +1952,25 @@ void ModuloSchedulingPass::reconstructLoop(MachineBasicBlock *BB) {
|
||||
llvm_epilogues[I]);
|
||||
|
||||
}
|
||||
else {
|
||||
MachineBasicBlock *origBlock = (MachineBasicBlock*) BB;
|
||||
for(MachineBasicBlock::reverse_iterator inst = origBlock->rbegin(), instEnd = origBlock->rend(); inst != instEnd; ++inst) {
|
||||
MachineOpCode OC = inst->getOpcode();
|
||||
if(TMI->isBranch(OC)) {
|
||||
branch = &*inst;
|
||||
DEBUG(std::cerr << "Exit branch from loop" << *inst << "\n");
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
for(unsigned opNum = 0; opNum < branch->getNumOperands(); ++opNum) {
|
||||
MachineOperand &mOp = branch->getOperand(opNum);
|
||||
|
||||
if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
|
||||
BuildMI(epilogues[I], V9::BA, 1).addPCDisp(mOp.getVRegValue());
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
else {
|
||||
BuildMI(epilogues[I], V9::BA, 1).addPCDisp(origBAVal);
|
||||
|
||||
|
||||
//Update last epilogue exit branch
|
||||
BranchInst *branchVal = (BranchInst*) dyn_cast<BranchInst>(BB->getBasicBlock()->getTerminator());
|
||||
//Find where we are supposed to branch to
|
||||
BasicBlock *nextBlock = 0;
|
||||
for(unsigned j=0; j <branchVal->getNumSuccessors(); ++j) {
|
||||
if(branchVal->getSuccessor(j) != BB->getBasicBlock())
|
||||
nextBlock = branchVal->getSuccessor(j);
|
||||
}
|
||||
TerminatorInst *newBranch = new BranchInst(nextBlock, llvm_epilogues[I]);
|
||||
}
|
||||
//Add one more nop!
|
||||
BuildMI(epilogues[I], V9::NOP, 0);
|
||||
|
||||
//Update last epilogue exit branch
|
||||
BranchInst *branchVal = (BranchInst*) dyn_cast<BranchInst>(BB->getBasicBlock()->getTerminator());
|
||||
//Find where we are supposed to branch to
|
||||
BasicBlock *nextBlock = 0;
|
||||
for(unsigned j=0; j <branchVal->getNumSuccessors(); ++j) {
|
||||
if(branchVal->getSuccessor(j) != BB->getBasicBlock())
|
||||
nextBlock = branchVal->getSuccessor(j);
|
||||
}
|
||||
|
||||
assert((nextBlock != 0) && "Next block should not be null!");
|
||||
TerminatorInst *newBranch = new BranchInst(nextBlock, llvm_epilogues[I]);
|
||||
}
|
||||
//Add one more nop!
|
||||
BuildMI(epilogues[I], V9::NOP, 0);
|
||||
|
||||
}
|
||||
|
||||
//FIX UP Machine BB entry!!
|
||||
|
||||
Loading…
Reference in New Issue
Block a user