From a65568676d0d9d53dd4aae8f1c58271bb4cfff10 Mon Sep 17 00:00:00 2001
From: Bill Wendling <isanbard@gmail.com>
Date: Sat, 11 Sep 2010 00:13:50 +0000
Subject: [PATCH] Rename ConvertToSetZeroFlag to something more general.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113670 91177308-0d34-0410-b5e6-96231b3b80d8
---
 include/llvm/Target/TargetInstrInfo.h | 9 +++++----
 lib/CodeGen/PeepholeOptimizer.cpp     | 4 ++--
 lib/Target/ARM/ARMBaseInstrInfo.cpp   | 4 ++--
 lib/Target/ARM/ARMBaseInstrInfo.h     | 4 ++--
 4 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 29fbe8217fe..6913fb8093e 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -585,10 +585,11 @@ public:
     return false;
   }
 
-  /// ConvertToSetZeroFlag - Convert the instruction supplying the argument to
-  /// the comparison into one that sets the zero bit in the flags
-  /// register. Update the iterator *only* if a transformation took place.
-  virtual bool ConvertToSetZeroFlag(MachineInstr * /*CmpInstr*/,
+  /// OptimizeCompareInstr - See if the comparison instruction can be converted
+  /// into something more efficient. E.g., on ARM most instructions can set the
+  /// flags register, obviating the need for a separate CMP. Update the iterator
+  /// *only* if a transformation took place.
+  virtual bool OptimizeCompareInstr(MachineInstr * /*CmpInstr*/,
                                     unsigned /*SrcReg*/, int /*CmpValue*/,
                                     MachineBasicBlock::iterator &) const {
     return false;
diff --git a/lib/CodeGen/PeepholeOptimizer.cpp b/lib/CodeGen/PeepholeOptimizer.cpp
index 529f994f003..15ede91a38e 100644
--- a/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/lib/CodeGen/PeepholeOptimizer.cpp
@@ -243,8 +243,8 @@ bool PeepholeOptimizer::OptimizeCmpInstr(MachineInstr *MI,
       TargetRegisterInfo::isPhysicalRegister(SrcReg))
     return false;
 
-  // Attempt to convert the defining instruction to set the "zero" flag.
-  if (TII->ConvertToSetZeroFlag(MI, SrcReg, CmpValue, NextIter)) {
+  // Attempt to optimize the comparison instruction.
+  if (TII->OptimizeCompareInstr(MI, SrcReg, CmpValue, NextIter)) {
     ++NumEliminated;
     return true;
   }
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index d79905a80b9..39feec99890 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1377,11 +1377,11 @@ AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpValue) const {
   return false;
 }
 
-/// ConvertToSetZeroFlag - Convert the instruction supplying the argument to the
+/// OptimizeCompareInstr - Convert the instruction supplying the argument to the
 /// comparison into one that sets the zero bit in the flags register. Update the
 /// iterator *only* if a transformation took place.
 bool ARMBaseInstrInfo::
-ConvertToSetZeroFlag(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue,
+OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue,
                      MachineBasicBlock::iterator &MII) const {
   if (CmpValue != 0)
     return false;
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h
index e76e2fe4023..207125e2443 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -344,9 +344,9 @@ public:
   virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
                               int &CmpValue) const;
 
-  /// ConvertToSetZeroFlag - Convert the instruction to set the zero flag so
+  /// OptimizeCompareInstr - Convert the instruction to set the zero flag so
   /// that we can remove a "comparison with zero".
-  virtual bool ConvertToSetZeroFlag(MachineInstr *CmpInstr, unsigned SrcReg,
+  virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
                                     int CmpValue,
                                     MachineBasicBlock::iterator &MII) const;