diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 4b1f4a71532..c30bf697623 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -1445,7 +1445,7 @@ defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si, // Store doubleword let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs), - (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr), + (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr), IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>; // Indexed stores diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index a8c9cdc610f..05e0b2b574e 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -2805,6 +2805,9 @@ _func: strd r0, r1, [r2, #-0] strd r0, r1, [r2, #-0]! strd r0, r1, [r2], #-0 + strd r0, r1, [r2, #256] + strd r0, r1, [r2, #256]! + strd r0, r1, [r2], #256 @ CHECK: strd r3, r5, [r6, #24] @ encoding: [0xc6,0xe9,0x06,0x35] @ CHECK: strd r3, r5, [r6, #24]! @ encoding: [0xe6,0xe9,0x06,0x35] @@ -2815,6 +2818,9 @@ _func: @ CHECK: strd r0, r1, [r2, #-0] @ encoding: [0x42,0xe9,0x00,0x01] @ CHECK: strd r0, r1, [r2, #-0]! @ encoding: [0x62,0xe9,0x00,0x01] @ CHECK: strd r0, r1, [r2], #-0 @ encoding: [0x62,0xe8,0x00,0x01] +@ CHECK: strd r0, r1, [r2, #256] @ encoding: [0xc2,0xe9,0x40,0x01] +@ CHECK: strd r0, r1, [r2, #256]! @ encoding: [0xe2,0xe9,0x40,0x01] +@ CHECK: strd r0, r1, [r2], #256 @ encoding: [0xe2,0xe8,0x40,0x01] @------------------------------------------------------------------------------ diff --git a/test/MC/ARM/thumb2-strd.s b/test/MC/ARM/thumb2-strd.s new file mode 100644 index 00000000000..3f8025d2cd7 --- /dev/null +++ b/test/MC/ARM/thumb2-strd.s @@ -0,0 +1,10 @@ +@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s +.text +.thumb + +@ CHECK: error: invalid operand for instruction +@ CHECK: error: invalid operand for instruction +@ CHECK: error: invalid operand for instruction +strd r12, SP, [r0, #256] +strd r12, SP, [r0, #256]! +strd r12, SP, [r0], #256