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Improve ISD::Constant codegen.

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Now for int foo() { return -1; } we generate:
_foo:
        li r3, -1
        blr

instead of
_foo:
        lis r2, -1
        ori r3, r2, 65535
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22864 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-08-18 18:01:39 +00:00
parent 36b708f057
commit a694047813
2 changed files with 13 additions and 9 deletions
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20
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -277,15 +277,18 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
case ISD::Constant: { case ISD::Constant: {
assert(N->getValueType(0) == MVT::i32); assert(N->getValueType(0) == MVT::i32);
unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue(); unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
if ((unsigned)(short)v == v) { unsigned Hi = HA16(v);
CurDAG->SelectNodeTo(N, MVT::i32, PPC::LI, getI32Imm(v)); unsigned Lo = Lo16(v);
break; if (Hi && Lo) {
} else { SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32, getI32Imm(v >> 16));
getI32Imm(unsigned(v) >> 16));
CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF)); CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
break; } else if (Lo) {
CurDAG->SelectNodeTo(N, MVT::i32, PPC::LI, getI32Imm(v));
} else {
CurDAG->SelectNodeTo(N, MVT::i32, PPC::LIS, getI32Imm(v >> 16));
} }
break;
} }
case ISD::SIGN_EXTEND_INREG: case ISD::SIGN_EXTEND_INREG:
switch(cast<VTSDNode>(N->getOperand(1))->getVT()) { switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
@ -412,12 +415,13 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
Select(N->getOperand(1))); Select(N->getOperand(1)));
break; break;
case ISD::AND: { case ISD::AND: {
unsigned Imm, SH, MB, ME; unsigned Imm;
// If this is an and of a value rotated between 0 and 31 bits and then and'd // If this is an and of a value rotated between 0 and 31 bits and then and'd
// with a mask, emit rlwinm // with a mask, emit rlwinm
if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) || if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
isShiftedMask_32(~Imm))) { isShiftedMask_32(~Imm))) {
SDOperand Val; SDOperand Val;
unsigned SH, MB, ME;
if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) { if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
Val = Select(N->getOperand(0).getOperand(0)); Val = Select(N->getOperand(0).getOperand(0));
} else { } else {

2
lib/Target/PowerPC/PPCISelPattern.cpp
View File

@ -1736,7 +1736,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
assert(N.getValueType() == MVT::i32 && assert(N.getValueType() == MVT::i32 &&
"Only i32 constants are legal on this target!"); "Only i32 constants are legal on this target!");
int v = (int)cast<ConstantSDNode>(N)->getValue(); int v = (int)cast<ConstantSDNode>(N)->getValue();
unsigned Hi = Hi16(v); unsigned Hi = HA16(v);
unsigned Lo = Lo16(v); unsigned Lo = Lo16(v);
if (Hi && Lo) { if (Hi && Lo) {
Tmp1 = MakeIntReg(); Tmp1 = MakeIntReg();