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[mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192438 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
4fa2c32220
commit
a6e253ddd0
@ -297,6 +297,13 @@ def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
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def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt),
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(fsub node:$wd, (fmul node:$ws, node:$wt))>;
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def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
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(add node:$wd, (mul node:$ws, node:$wt))>;
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def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
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(sub node:$wd, (mul node:$ws, node:$wt))>;
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// Immediates
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def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>;
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def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
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@ -2021,14 +2028,10 @@ class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h,
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class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w,
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MSA128WOpnd>;
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class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", int_mips_maddv_b,
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MSA128BOpnd>;
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class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", int_mips_maddv_h,
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MSA128HOpnd>;
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class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", int_mips_maddv_w,
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MSA128WOpnd>;
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class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", int_mips_maddv_d,
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MSA128DOpnd>;
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class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>;
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class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>;
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class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>;
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class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>;
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class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>;
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class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>;
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@ -2124,14 +2127,10 @@ class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h,
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class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w,
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MSA128WOpnd>;
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class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", int_mips_msubv_b,
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MSA128BOpnd>;
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class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", int_mips_msubv_h,
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MSA128HOpnd>;
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class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", int_mips_msubv_w,
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MSA128WOpnd>;
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class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", int_mips_msubv_d,
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MSA128DOpnd>;
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class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>;
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class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>;
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class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>;
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class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>;
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class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h,
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MSA128HOpnd>;
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@ -1401,6 +1401,15 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
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case Intrinsic::mips_ldi_w:
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case Intrinsic::mips_ldi_d:
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return lowerMSASplatImm(Op, 1, DAG);
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case Intrinsic::mips_maddv_b:
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case Intrinsic::mips_maddv_h:
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case Intrinsic::mips_maddv_w:
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case Intrinsic::mips_maddv_d: {
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EVT ResTy = Op->getValueType(0);
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return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
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DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
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Op->getOperand(2), Op->getOperand(3)));
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}
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case Intrinsic::mips_max_s_b:
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case Intrinsic::mips_max_s_h:
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case Intrinsic::mips_max_s_w:
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@ -1467,6 +1476,15 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
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case Intrinsic::mips_mulv_d:
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return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
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Op->getOperand(2));
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case Intrinsic::mips_msubv_b:
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case Intrinsic::mips_msubv_h:
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case Intrinsic::mips_msubv_w:
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case Intrinsic::mips_msubv_d: {
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EVT ResTy = Op->getValueType(0);
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return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
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DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
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Op->getOperand(2), Op->getOperand(3)));
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}
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case Intrinsic::mips_nlzc_b:
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case Intrinsic::mips_nlzc_h:
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case Intrinsic::mips_nlzc_w:
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@ -308,6 +308,166 @@ define void @mul_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
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; CHECK: .size mul_v2i64
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}
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define void @maddv_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
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<16 x i8>* %c) nounwind {
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; CHECK: maddv_v16i8:
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%1 = load <16 x i8>* %a
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; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
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%2 = load <16 x i8>* %b
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; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
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%3 = load <16 x i8>* %c
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; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
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%4 = mul <16 x i8> %2, %3
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%5 = add <16 x i8> %4, %1
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; CHECK-DAG: maddv.b [[R1]], [[R2]], [[R3]]
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store <16 x i8> %5, <16 x i8>* %d
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; CHECK-DAG: st.b [[R1]], 0($4)
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ret void
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; CHECK: .size maddv_v16i8
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}
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define void @maddv_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
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<8 x i16>* %c) nounwind {
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; CHECK: maddv_v8i16:
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%1 = load <8 x i16>* %a
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; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
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%2 = load <8 x i16>* %b
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; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
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%3 = load <8 x i16>* %c
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; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)
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%4 = mul <8 x i16> %2, %3
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%5 = add <8 x i16> %4, %1
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; CHECK-DAG: maddv.h [[R1]], [[R2]], [[R3]]
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store <8 x i16> %5, <8 x i16>* %d
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; CHECK-DAG: st.h [[R1]], 0($4)
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ret void
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; CHECK: .size maddv_v8i16
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}
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define void @maddv_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
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<4 x i32>* %c) nounwind {
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; CHECK: maddv_v4i32:
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%1 = load <4 x i32>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x i32>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = load <4 x i32>* %c
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; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
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%4 = mul <4 x i32> %2, %3
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%5 = add <4 x i32> %4, %1
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; CHECK-DAG: maddv.w [[R1]], [[R2]], [[R3]]
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store <4 x i32> %5, <4 x i32>* %d
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; CHECK-DAG: st.w [[R1]], 0($4)
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ret void
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; CHECK: .size maddv_v4i32
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}
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define void @maddv_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
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<2 x i64>* %c) nounwind {
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; CHECK: maddv_v2i64:
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%1 = load <2 x i64>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x i64>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = load <2 x i64>* %c
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; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
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%4 = mul <2 x i64> %2, %3
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%5 = add <2 x i64> %4, %1
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; CHECK-DAG: maddv.d [[R1]], [[R2]], [[R3]]
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store <2 x i64> %5, <2 x i64>* %d
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; CHECK-DAG: st.d [[R1]], 0($4)
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ret void
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; CHECK: .size maddv_v2i64
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}
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define void @msubv_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
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<16 x i8>* %c) nounwind {
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; CHECK: msubv_v16i8:
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%1 = load <16 x i8>* %a
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; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
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%2 = load <16 x i8>* %b
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; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
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%3 = load <16 x i8>* %c
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; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
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%4 = mul <16 x i8> %2, %3
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%5 = sub <16 x i8> %1, %4
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; CHECK-DAG: msubv.b [[R1]], [[R2]], [[R3]]
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store <16 x i8> %5, <16 x i8>* %d
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; CHECK-DAG: st.b [[R1]], 0($4)
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ret void
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; CHECK: .size msubv_v16i8
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}
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define void @msubv_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
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<8 x i16>* %c) nounwind {
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; CHECK: msubv_v8i16:
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%1 = load <8 x i16>* %a
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; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
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%2 = load <8 x i16>* %b
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; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
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%3 = load <8 x i16>* %c
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; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)
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%4 = mul <8 x i16> %2, %3
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%5 = sub <8 x i16> %1, %4
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; CHECK-DAG: msubv.h [[R1]], [[R2]], [[R3]]
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store <8 x i16> %5, <8 x i16>* %d
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; CHECK-DAG: st.h [[R1]], 0($4)
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ret void
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; CHECK: .size msubv_v8i16
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}
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define void @msubv_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
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<4 x i32>* %c) nounwind {
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; CHECK: msubv_v4i32:
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%1 = load <4 x i32>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x i32>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = load <4 x i32>* %c
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; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
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%4 = mul <4 x i32> %2, %3
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%5 = sub <4 x i32> %1, %4
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; CHECK-DAG: msubv.w [[R1]], [[R2]], [[R3]]
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store <4 x i32> %5, <4 x i32>* %d
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; CHECK-DAG: st.w [[R1]], 0($4)
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ret void
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; CHECK: .size msubv_v4i32
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}
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define void @msubv_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
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<2 x i64>* %c) nounwind {
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; CHECK: msubv_v2i64:
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%1 = load <2 x i64>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x i64>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = load <2 x i64>* %c
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; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
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%4 = mul <2 x i64> %2, %3
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%5 = sub <2 x i64> %1, %4
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; CHECK-DAG: msubv.d [[R1]], [[R2]], [[R3]]
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store <2 x i64> %5, <2 x i64>* %d
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; CHECK-DAG: st.d [[R1]], 0($4)
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ret void
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; CHECK: .size msubv_v2i64
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}
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define void @div_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
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; CHECK: div_s_v16i8:
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