From a6e734d2ed962c914005e9a5fe8a14fbc9707884 Mon Sep 17 00:00:00 2001 From: Quentin Colombet Date: Sat, 22 Feb 2014 01:06:41 +0000 Subject: [PATCH] [CodeGenPrepare] Fix the check of the legality of an instruction. The API expects an ISD opcode, not an IR opcode. Fixes a regression for R600. Related to . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201923 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/CodeGenPrepare.cpp | 7 ++++++- test/CodeGen/R600/codegen-prepare-addrmode-sext.ll | 11 +++++++---- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/lib/CodeGen/CodeGenPrepare.cpp b/lib/CodeGen/CodeGenPrepare.cpp index e81a9098ef5..0c765b64313 100644 --- a/lib/CodeGen/CodeGenPrepare.cpp +++ b/lib/CodeGen/CodeGenPrepare.cpp @@ -1756,7 +1756,12 @@ AddressingModeMatcher::IsPromotionProfitable(unsigned MatchedSize, Instruction *PromotedInst = dyn_cast(PromotedOperand); if (!PromotedInst) return false; - return TLI.isOperationLegalOrCustom(PromotedInst->getOpcode(), + int ISDOpcode = TLI.InstructionOpcodeToISD(PromotedInst->getOpcode()); + // If the ISDOpcode is undefined, it was undefined before the promotion. + if (!ISDOpcode) + return true; + // Otherwise, check if the promoted instruction is legal or not. + return TLI.isOperationLegalOrCustom(ISDOpcode, EVT::getEVT(PromotedInst->getType())); } diff --git a/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll b/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll index 6c8b26a3ae9..f8b4a61a7db 100644 --- a/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll +++ b/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll @@ -1,11 +1,14 @@ -; RUN: opt -codegenprepare -S -o - %s | FileCheck %s +; RUN: opt -codegenprepare -S -o - %s | FileCheck --check-prefix=OPT --check-prefix=FUNC %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-LLC --check-prefix=FUNC %s target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" target triple = "r600--" -; CHECK-LABEL: @test -; CHECK: mul -; CHECK-NEXT: sext +; FUNC-LABEL: @test +; OPT: mul nsw i32 +; OPT-NEXT: sext +; SI-LLC: V_MUL_LO_I32 +; SI-LLC-NOT: V_MUL_HI define void @test(i8 addrspace(1)* nocapture readonly %in, i32 %a, i8 %b) { entry: %0 = mul nsw i32 %a, 3