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Fix Mips, Sparc, and XCore tests that were dependent on register allocation.

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Add an extra run with -regalloc=basic to keep them honest.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128654 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2011-03-31 18:42:43 +00:00
parent 1d6b38d9d3
commit a6f7499244
6 changed files with 60 additions and 49 deletions
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test/CodeGen/XCore/mul64.ll
+17 -16
View File
@@ -1,4 +1,5 @@
; RUN: llc < %s -march=xcore | FileCheck %s
; RUN: llc < %s -march=xcore -regalloc=basic | FileCheck %s
define i64 @umul_lohi(i32 %a, i32 %b) {
entry:
%0 = zext i32 %a to i64
@@ -7,8 +8,8 @@ entry:
ret i64 %2
}
; CHECK: umul_lohi:
; CHECK: ldc r2, 0
; CHECK-NEXT: lmul r1, r0, r1, r0, r2, r2
; CHECK: ldc [[REG:r[0-9]+]], 0
; CHECK-NEXT: lmul r1, r0, r1, r0, [[REG]], [[REG]]
; CHECK-NEXT: retsp 0
define i64 @smul_lohi(i32 %a, i32 %b) {
@@ -19,11 +20,11 @@ entry:
ret i64 %2
}
; CHECK: smul_lohi:
; CHECK: ldc r2, 0
; CHECK-NEXT: mov r3, r2
; CHECK-NEXT: maccs r2, r3, r1, r0
; CHECK-NEXT: mov r0, r3
; CHECK-NEXT: mov r1, r2
; CHECK: ldc
; CHECK-NEXT: mov
; CHECK-NEXT: maccs
; CHECK-NEXT: mov r0,
; CHECK-NEXT: mov r1,
; CHECK-NEXT: retsp 0
define i64 @mul64(i64 %a, i64 %b) {
@@ -32,11 +33,11 @@ entry:
ret i64 %0
}
; CHECK: mul64:
; CHECK: ldc r11, 0
; CHECK-NEXT: lmul r11, r4, r0, r2, r11, r11
; CHECK-NEXT: mul r0, r0, r3
; CHECK-NEXT: lmul r0, r1, r1, r2, r11, r0
; CHECK-NEXT: mov r0, r4
; CHECK: ldc
; CHECK-NEXT: lmul
; CHECK-NEXT: mul
; CHECK-NEXT: lmul
; CHECK-NEXT: mov r0,
define i64 @mul64_2(i64 %a, i32 %b) {
entry:
@@ -45,8 +46,8 @@ entry:
ret i64 %1
}
; CHECK: mul64_2:
; CHECK: ldc r3, 0
; CHECK-NEXT: lmul r3, r0, r0, r2, r3, r3
; CHECK-NEXT: mul r1, r1, r2
; CHECK-NEXT: add r1, r3, r1
; CHECK: ldc
; CHECK-NEXT: lmul
; CHECK-NEXT: mul
; CHECK-NEXT: add r1,
; CHECK-NEXT: retsp 0