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[Hexagon] Adding zxtb instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222660 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-11-24 16:48:43 +00:00
parent a17a9dc8df
commit a723df08bb
3 changed files with 53 additions and 5 deletions
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8
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -717,7 +717,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
case Hexagon::ASRH:
case Hexagon::A2_sxtb:
case Hexagon::A2_sxth:
case Hexagon::ZXTB:
case Hexagon::A2_zxtb:
case Hexagon::ZXTH:
return Subtarget.hasV4TOps();
}
@ -1323,6 +1323,10 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
case Hexagon::A4_psxtbfnew:
case Hexagon::A4_psxtbt:
case Hexagon::A4_psxtbtnew:
case Hexagon::A4_pzxtbf:
case Hexagon::A4_pzxtbfnew:
case Hexagon::A4_pzxtbt:
case Hexagon::A4_pzxtbtnew:
case Hexagon::ADD_ri_cPt:
case Hexagon::ADD_ri_cNotPt:
case Hexagon::COMBINE_rr_cPt:
@ -1332,8 +1336,6 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
case Hexagon::ASLH_cNotPt_V4:
case Hexagon::ASRH_cPt_V4:
case Hexagon::ASRH_cNotPt_V4:
case Hexagon::ZXTB_cPt_V4:
case Hexagon::ZXTB_cNotPt_V4:
case Hexagon::ZXTH_cPt_V4:
case Hexagon::ZXTH_cNotPt_V4:
return QRI.Subtarget.hasV4TOps();

40
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -268,6 +268,43 @@ multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
// Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
// Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
// predicated forms while 'and' doesn't. Since integrated assembler can't
// handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
// immediate operand is set to '255'.
let hasNewValue = 1, opNewValue = 0 in
class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
"$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
bits<5> Rd;
bits<5> Rs;
bits<10> s10 = 255;
let IClass = 0b0111;
let Inst{27-22} = 0b011000;
let Inst{4-0} = Rd;
let Inst{20-16} = Rs;
let Inst{21} = s10{9};
let Inst{13-5} = s10{8-0};
}
//Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
let BaseOpcode = mnemonic in {
let isPredicable = 1, hasSideEffects = 0 in
def A2_#NAME : T_ZXTB;
let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
}
}
}
defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
// Combines the two integer registers SRC1 and SRC2 into a double register.
let isPredicable = 1 in
class T_Combine : ALU32_rr<(outs DoubleRegs:$dst),
@ -598,7 +635,6 @@ multiclass ALU32_2op_base2<string mnemonic> {
defm ASLH : ALU32_2op_base2<"aslh">, PredNewRel;
defm ASRH : ALU32_2op_base2<"asrh">, PredNewRel;
defm ZXTB : ALU32_2op_base2<"zxtb">, PredNewRel;
defm ZXTH : ALU32_2op_base2<"zxth">, PredNewRel;
def : Pat <(shl (i32 IntRegs:$src1), (i32 16)),
@ -2288,7 +2324,7 @@ def : Pat <(and (i32 IntRegs:$src1), 65535),
// Map from r0 = and(r1, 255) to r0 = zxtb(r1).
def : Pat <(and (i32 IntRegs:$src1), 255),
(ZXTB (i32 IntRegs:$src1))>;
(A2_zxtb (i32 IntRegs:$src1))>;
// Map Add(p1, true) to p1 = not(p1).
// Add(p1, false) should never be produced,

10
test/MC/Hexagon/inst_zxtb.ll Normal file
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@ -0,0 +1,10 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -s - | FileCheck %s
define i32 @foo (i8 %a)
{
%1 = zext i8 %a to i32
ret i32 %1
}
; CHECK: 0000 e05f0076 00c09f52