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Add a nasty hack to fix Alpha/IA64 multiplies by a power of two.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19737 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-01-22 00:20:42 +00:00
parent 9bb86f46e1
commit a7306db5f7
1 changed files with 9 additions and 4 deletions
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13
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -446,6 +446,7 @@ SDOperand SelectionDAG::getSetCC(ISD::CondCode Cond, MVT::ValueType VT,
else { else {
assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
// (Z-X) == X --> Z == X<<1 // (Z-X) == X --> Z == X<<1
if (N2.getValueType() != MVT::i64) // FIXME: HACK HACK HACK!
return getSetCC(Cond, VT, N1.getOperand(0), return getSetCC(Cond, VT, N1.getOperand(0),
getNode(ISD::SHL, N2.getValueType(), getNode(ISD::SHL, N2.getValueType(),
N2, getConstant(1, MVT::i8))); N2, getConstant(1, MVT::i8)));
@ -654,8 +655,10 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
// FIXME: This should only be done if the target supports shift // FIXME: This should only be done if the target supports shift
// operations. // operations.
if ((C2 & C2-1) == 0) { if ((C2 & C2-1) == 0) {
SDOperand ShAmt = getConstant(ExactLog2(C2), MVT::i8); if (N2.getValueType() != MVT::i64) { // FIXME: HACK HACK HACK!
return getNode(ISD::SHL, VT, N1, ShAmt); SDOperand ShAmt = getConstant(ExactLog2(C2), MVT::i8);
return getNode(ISD::SHL, VT, N1, ShAmt);
}
} }
break; break;
@ -663,8 +666,10 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
// FIXME: This should only be done if the target supports shift // FIXME: This should only be done if the target supports shift
// operations. // operations.
if ((C2 & C2-1) == 0 && C2) { if ((C2 & C2-1) == 0 && C2) {
SDOperand ShAmt = getConstant(ExactLog2(C2), MVT::i8); if (N2.getValueType() != MVT::i64) { // FIXME: HACK HACK HACK!
return getNode(ISD::SRL, VT, N1, ShAmt); SDOperand ShAmt = getConstant(ExactLog2(C2), MVT::i8);
return getNode(ISD::SRL, VT, N1, ShAmt);
}
} }
break; break;