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https://github.com/c64scene-ar/llvm-6502.git
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more flags set right
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45860 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -526,6 +526,7 @@ let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
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def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
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def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
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"shl{q}\t{$src2, $dst|$dst, $src2}",
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"shl{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
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[(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
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let neverHasSideEffects = 1 in
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def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
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def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
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"shl{q}\t$dst", []>;
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"shl{q}\t$dst", []>;
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} // isTwoAddress
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} // isTwoAddress
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@ -166,6 +166,7 @@ class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
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FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;
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FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;
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// Register copies. Just copies, the shortening ones do not truncate.
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// Register copies. Just copies, the shortening ones do not truncate.
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let neverHasSideEffects = 1 in {
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def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>;
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def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>;
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def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>;
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def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>;
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def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>;
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def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>;
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@ -175,6 +176,7 @@ def MOV_Fp3280 : FpIf32<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []
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def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
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def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
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def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
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def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
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def MOV_Fp8080 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
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def MOV_Fp8080 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
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}
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// Factoring for arithmetic.
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// Factoring for arithmetic.
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multiclass FPBinary_rr<SDNode OpNode> {
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multiclass FPBinary_rr<SDNode OpNode> {
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@ -293,12 +295,11 @@ defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
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defm SIN : FPUnary<fsin, 0xFE, "fsin">;
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defm SIN : FPUnary<fsin, 0xFE, "fsin">;
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defm COS : FPUnary<fcos, 0xFF, "fcos">;
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defm COS : FPUnary<fcos, 0xFF, "fcos">;
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def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP,
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let neverHasSideEffects = 1 in {
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[]>;
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def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;
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def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP,
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def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
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[]>;
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def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
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def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP,
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}
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[]>;
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def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
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def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
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// Floating point cmovs.
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// Floating point cmovs.
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@ -392,7 +393,7 @@ def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
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[(truncstoref64 RFP80:$src, addr:$op)]>;
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[(truncstoref64 RFP80:$src, addr:$op)]>;
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// FST does not support 80-bit memory target; FSTP must be used.
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// FST does not support 80-bit memory target; FSTP must be used.
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let mayStore = 1 in {
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let mayStore = 1, neverHasSideEffects = 1 in {
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def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
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def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
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def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
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def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
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def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
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def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
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@ -401,7 +402,7 @@ def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
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}
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}
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def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
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def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
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[(store RFP80:$src, addr:$op)]>;
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[(store RFP80:$src, addr:$op)]>;
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let mayStore = 1 in {
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let mayStore = 1, neverHasSideEffects = 1 in {
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def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
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def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
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def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
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def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
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def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
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def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
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@ -498,17 +499,18 @@ def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
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// Floating point compares.
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// Floating point compares.
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let Defs = [EFLAGS] in {
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let Defs = [EFLAGS] in {
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def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
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def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
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[]>; // FPSW = cmp ST(0) with ST(i)
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[]>; // FPSW = cmp ST(0) with ST(i)
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def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
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[]>; // FPSW = cmp ST(0) with ST(i)
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def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
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[]>; // FPSW = cmp ST(0) with ST(i)
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def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
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def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
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[(X86cmp RFP32:$lhs, RFP32:$rhs),
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[(X86cmp RFP32:$lhs, RFP32:$rhs),
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(implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
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(implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
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def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
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[]>; // FPSW = cmp ST(0) with ST(i)
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def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
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def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
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[(X86cmp RFP64:$lhs, RFP64:$rhs),
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[(X86cmp RFP64:$lhs, RFP64:$rhs),
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(implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
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(implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
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def UCOM_Fpr80 : FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
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[]>; // FPSW = cmp ST(0) with ST(i)
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def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
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def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
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[(X86cmp RFP80:$lhs, RFP80:$rhs),
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[(X86cmp RFP80:$lhs, RFP80:$rhs),
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(implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
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(implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
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@ -419,6 +419,7 @@ let isTwoAddress = 1 in // GR32 = bswap GR32
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[(set GR32:$dst, (bswap GR32:$src))]>, TB;
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[(set GR32:$dst, (bswap GR32:$src))]>, TB;
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// FIXME: Model xchg* as two address instructions?
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// FIXME: Model xchg* as two address instructions?
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let neverHasSideEffects = 1 in {
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def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8
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def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8
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(outs), (ins GR8:$src1, GR8:$src2),
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(outs), (ins GR8:$src1, GR8:$src2),
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"xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
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"xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
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@ -428,7 +429,9 @@ def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16
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def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32
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def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32
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(outs), (ins GR32:$src1, GR32:$src2),
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(outs), (ins GR32:$src1, GR32:$src2),
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"xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
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"xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
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}
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let mayLoad = 1, mayStore = 1 in {
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def XCHG8mr : I<0x86, MRMDestMem,
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def XCHG8mr : I<0x86, MRMDestMem,
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(outs), (ins i8mem:$src1, GR8:$src2),
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(outs), (ins i8mem:$src1, GR8:$src2),
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"xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
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"xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
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@ -447,6 +450,7 @@ def XCHG16rm : I<0x87, MRMSrcMem,
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def XCHG32rm : I<0x87, MRMSrcMem,
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def XCHG32rm : I<0x87, MRMSrcMem,
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(outs), (ins GR32:$src1, i32mem:$src2),
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(outs), (ins GR32:$src1, i32mem:$src2),
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"xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
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"xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
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}
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// Bit scan instructions.
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// Bit scan instructions.
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let Defs = [EFLAGS] in {
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let Defs = [EFLAGS] in {
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@ -621,10 +625,10 @@ def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
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// This probably ought to be moved to a def : Pat<> if the
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// This probably ought to be moved to a def : Pat<> if the
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// syntax can be accepted.
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// syntax can be accepted.
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[(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
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[(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
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let Defs = [AX,DX,EFLAGS], Uses = [AX] in
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let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
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def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
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def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
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OpSize; // AX,DX = AX*GR16
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OpSize; // AX,DX = AX*GR16
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
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def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
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def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
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// EAX,EDX = EAX*GR32
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// EAX,EDX = EAX*GR32
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let Defs = [AL,AH,EFLAGS], Uses = [AL] in
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let Defs = [AL,AH,EFLAGS], Uses = [AL] in
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@ -1416,12 +1420,14 @@ def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
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}
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}
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// Shift left by one. Not used because (add x, x) is slightly cheaper.
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// Shift left by one. Not used because (add x, x) is slightly cheaper.
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let neverHasSideEffects = 1 in {
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def SHL8r1 : I<0xD0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
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def SHL8r1 : I<0xD0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
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"shl{b}\t$dst", []>;
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"shl{b}\t$dst", []>;
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def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
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def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
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"shl{w}\t$dst", []>, OpSize;
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"shl{w}\t$dst", []>, OpSize;
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def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
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def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
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"shl{l}\t$dst", []>;
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"shl{l}\t$dst", []>;
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}
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let isTwoAddress = 0 in {
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let isTwoAddress = 0 in {
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let Uses = [CL] in {
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let Uses = [CL] in {
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