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Fix broken FileCheck prefixes

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209538 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nico Rieck 2014-05-23 19:06:24 +00:00
parent 8d959dd563
commit a739ea33a0
5 changed files with 14 additions and 14 deletions
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2
test/CodeGen/ARM64/cse.ll
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@ -13,7 +13,7 @@ entry:
; CHECK: b.ge
; CHECK: sub
; CHECK: sub
; CHECK_NOT: sub
; CHECK-NOT: sub
; CHECK: ret
%0 = load i32* %offset, align 4
%cmp = icmp slt i32 %0, %size

6
test/CodeGen/ARM64/csel.ll
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@ -79,9 +79,9 @@ define i32 @foo7(i32 %a, i32 %b) nounwind {
entry:
; CHECK-LABEL: foo7:
; CHECK: sub
; CHECK-next: adds
; CHECK-next: csneg
; CHECK-next: b
; CHECK-NEXT: adds
; CHECK-NEXT: csneg
; CHECK-NEXT: b
%sub = sub nsw i32 %a, %b
%cmp = icmp sgt i32 %sub, -1
%sub3 = sub nsw i32 0, %sub

16
test/CodeGen/ARM64/vmul.ll
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@ -1201,35 +1201,35 @@ define <2 x i64> @umlsl_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nou
; Scalar FMULX
define float @fmulxs(float %a, float %b) nounwind {
; CHECK-LABEL: fmulxs:
; CHECKNEXT: fmulx s0, s0, s1
; CHECK-NEXT: fmulx s0, s0, s1
%fmulx.i = tail call float @llvm.arm64.neon.fmulx.f32(float %a, float %b) nounwind
; CHECKNEXT: ret
; CHECK-NEXT: ret
ret float %fmulx.i
}
define double @fmulxd(double %a, double %b) nounwind {
; CHECK-LABEL: fmulxd:
; CHECKNEXT: fmulx d0, d0, d1
; CHECK-NEXT: fmulx d0, d0, d1
%fmulx.i = tail call double @llvm.arm64.neon.fmulx.f64(double %a, double %b) nounwind
; CHECKNEXT: ret
; CHECK-NEXT: ret
ret double %fmulx.i
}
define float @fmulxs_lane(float %a, <4 x float> %vec) nounwind {
; CHECK-LABEL: fmulxs_lane:
; CHECKNEXT: fmulx.s s0, s0, v1[3]
; CHECK-NEXT: fmulx.s s0, s0, v1[3]
%b = extractelement <4 x float> %vec, i32 3
%fmulx.i = tail call float @llvm.arm64.neon.fmulx.f32(float %a, float %b) nounwind
; CHECKNEXT: ret
; CHECK-NEXT: ret
ret float %fmulx.i
}
define double @fmulxd_lane(double %a, <2 x double> %vec) nounwind {
; CHECK-LABEL: fmulxd_lane:
; CHECKNEXT: fmulx d0, d0, v1[1]
; CHECK-NEXT: fmulx d0, d0, v1[1]
%b = extractelement <2 x double> %vec, i32 1
%fmulx.i = tail call double @llvm.arm64.neon.fmulx.f64(double %a, double %b) nounwind
; CHECKNEXT: ret
; CHECK-NEXT: ret
ret double %fmulx.i
}

2
test/CodeGen/MSP430/fp.ll
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@ -21,7 +21,7 @@ entry:
; does not happen anymore. Note that the only reason an ISR is used here is that
; the register allocator selects r4 first instead of fifth in a normal function.
define msp430_intrcc void @fpb_alloced() #0 {
; CHECK_LABEL: fpb_alloced:
; CHECK-LABEL: fpb_alloced:
; CHECK-NOT: mov.b #0, r4
; CHECK: nop
call void asm sideeffect "nop", "r"(i8 0)

2
test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll
View File

@ -223,7 +223,7 @@ define <4 x float> @reschedule_extract(<4 x float> %a, <4 x float> %b) {
; instructions that are erased.
define <4 x float> @take_credit(<4 x float> %a, <4 x float> %b) {
; ZEROTHRESH-LABEL: @take_credit(
; ZEROTHRESH-CHECK: %1 = fadd <4 x float> %a, %b
; ZEROTHRESH: %1 = fadd <4 x float> %a, %b
%a0 = extractelement <4 x float> %a, i32 0
%b0 = extractelement <4 x float> %b, i32 0
%c0 = fadd float %a0, %b0