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R600/SI: Add verifier check for immediates in register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212214 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -559,7 +559,14 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
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// Make sure the register classes are correct
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for (unsigned i = 0, e = Desc.getNumOperands(); i != e; ++i) {
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switch (Desc.OpInfo[i].OperandType) {
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case MCOI::OPERAND_REGISTER:
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case MCOI::OPERAND_REGISTER: {
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int RegClass = Desc.OpInfo[i].RegClass;
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if (!RI.regClassCanUseImmediate(RegClass) &&
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(MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm())) {
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ErrInfo = "Expected register, but got immediate";
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return false;
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}
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}
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break;
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case MCOI::OPERAND_IMMEDIATE:
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if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm()) {
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@ -1632,7 +1632,7 @@ let usesCustomInserter = 1 in {
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// constant that can be used with the ADDR64 MUBUF instructions.
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def SI_ADDR64_RSRC : InstSI <
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(outs SReg_128:$srsrc),
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(ins SReg_64:$ptr),
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(ins SSrc_64:$ptr),
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"", []
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>;
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@ -125,3 +125,19 @@ unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
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unsigned Index = getHWRegIndex(Reg);
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return SubRC->getRegister(Index + Channel);
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}
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bool SIRegisterInfo::regClassCanUseImmediate(int RCID) const {
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switch (RCID) {
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default: return false;
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case AMDGPU::SSrc_32RegClassID:
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case AMDGPU::SSrc_64RegClassID:
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case AMDGPU::VSrc_32RegClassID:
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case AMDGPU::VSrc_64RegClassID:
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return true;
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}
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}
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bool SIRegisterInfo::regClassCanUseImmediate(
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const TargetRegisterClass *RC) const {
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return regClassCanUseImmediate(RC->getID());
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}
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@ -60,6 +60,14 @@ struct SIRegisterInfo : public AMDGPURegisterInfo {
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/// \returns The sub-register of Reg that is in Channel.
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unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
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unsigned Channel) const;
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/// \returns True if operands defined with this register class can accept
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/// inline immediates.
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bool regClassCanUseImmediate(int RCID) const;
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/// \returns True if operands defined with this register class can accept
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/// inline immediates.
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bool regClassCanUseImmediate(const TargetRegisterClass *RC) const;
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};
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} // End namespace llvm
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