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https://github.com/c64scene-ar/llvm-6502.git
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ARMv7M vs. ARMv7E-M support.
The DSP instructions in the Thumb2 instruction set are an optional extension in the Cortex-M* archtitecture. When present, the implementation is considered an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation." Add a subtarget feature hook for the v7e-m instructions and hook it up. The cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is a v7e-m implementation. rdar://9572992 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
5b1b4489cf
commit
a7603982db
@ -75,6 +75,10 @@ def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
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"AvoidCPSRPartialUpdate", "true",
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"Avoid CPSR partial update for OOO execution">;
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/// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
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def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
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"Supports v7 DSP instructions in Thumb2.">;
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// Multiprocessing extension.
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def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
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"Supports Multiprocessing extension">;
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@ -93,14 +97,20 @@ def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
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[FeatureNoARM, FeatureDB]>;
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def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
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"ARM v6t2",
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[FeatureThumb2]>;
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[FeatureThumb2, FeatureDSPThumb2]>;
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def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
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"ARM v7A",
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[FeatureThumb2, FeatureNEON, FeatureDB]>;
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[FeatureThumb2, FeatureNEON, FeatureDB,
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FeatureDSPThumb2]>;
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def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
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"ARM v7M",
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[FeatureThumb2, FeatureNoARM, FeatureDB,
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FeatureHWDiv]>;
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def ArchV7EM : SubtargetFeature<"v7em", "ARMArchVersion", "V7EM",
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"ARM v7E-M",
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[FeatureThumb2, FeatureNoARM, FeatureDB,
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FeatureHWDiv, FeatureDSPThumb2,
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FeatureT2XtPk]>;
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//===----------------------------------------------------------------------===//
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// ARM Processors supported.
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@ -192,7 +202,7 @@ def : Processor<"cortex-a9-mp", CortexA9Itineraries,
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// V7M Processors.
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def : ProcNoItin<"cortex-m3", [ArchV7M]>;
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def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureVFP2, FeatureVFPOnlySP]>;
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def : ProcNoItin<"cortex-m4", [ArchV7EM, FeatureVFP2, FeatureVFPOnlySP]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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@ -541,7 +541,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
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}
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if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops())
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if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
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|| (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
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setOperationAction(ISD::MULHS, MVT::i32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
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@ -164,6 +164,8 @@ def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
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def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
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def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
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AssemblerPredicate;
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def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
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AssemblerPredicate;
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def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
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AssemblerPredicate;
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def HasMP : Predicate<"Subtarget->hasMPExtension()">,
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@ -1038,7 +1038,8 @@ multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
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// supported yet.
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multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
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def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
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opc, "\t$Rd, $Rm", []> {
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opc, "\t$Rd, $Rm", []>,
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Requires<[IsThumb2, HasT2ExtractPack]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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@ -1048,7 +1049,8 @@ multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
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let Inst{5-4} = 0b00; // rotate
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}
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def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
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opc, "\t$Rd, $Rm, ror $rot", []> {
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opc, "\t$Rd, $Rm, ror $rot", []>,
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Requires<[IsThumb2, HasT2ExtractPack]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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@ -1779,7 +1781,8 @@ def : T2Pat<(adde_live_carry rGPR:$src, t2_so_imm_not:$imm),
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// Select Bytes -- for disassembly only
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def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []> {
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NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-24} = 0b010;
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let Inst{23} = 0b1;
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@ -1795,7 +1798,8 @@ class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
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list<dag> pat = [/* For disassembly only; pattern left blank */],
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dag iops = (ins rGPR:$Rn, rGPR:$Rm),
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string asm = "\t$Rd, $Rn, $Rm">
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: T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat> {
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: T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0101;
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let Inst{22-20} = op22_20;
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@ -1893,12 +1897,14 @@ class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
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def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
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(ins rGPR:$Rn, rGPR:$Rm),
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NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []> {
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NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{15-12} = 0b1111;
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}
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def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
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(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
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"usada8", "\t$Rd, $Rn, $Rm, $Ra", []>;
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"usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
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Requires<[IsThumb2, HasThumb2DSP]>;
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// Signed/Unsigned saturate -- for disassembly only
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@ -1931,7 +1937,8 @@ def t2SSAT: T2SatI<
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def t2SSAT16: T2SatI<
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(outs rGPR:$Rd), (ins ssat_imm:$sat_imm, rGPR:$Rn), NoItinerary,
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"ssat16", "\t$Rd, $sat_imm, $Rn",
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[/* For disassembly only; pattern left blank */]> {
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[/* For disassembly only; pattern left blank */]>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11110;
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let Inst{25-22} = 0b1100;
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let Inst{20} = 0;
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@ -1954,7 +1961,8 @@ def t2USAT: T2SatI<
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def t2USAT16: T2SatI<(outs rGPR:$dst), (ins i32imm:$sat_imm, rGPR:$Rn),
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NoItinerary,
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"usat16", "\t$dst, $sat_imm, $Rn",
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[/* For disassembly only; pattern left blank */]> {
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[/* For disassembly only; pattern left blank */]>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11110;
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let Inst{25-22} = 0b1110;
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let Inst{20} = 0;
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@ -2225,7 +2233,8 @@ def t2UMLAL : T2MulLong<0b110, 0b0000,
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def t2UMAAL : T2MulLong<0b110, 0b0110,
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(outs rGPR:$RdLo, rGPR:$RdHi),
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(ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
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"umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
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"umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
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Requires<[IsThumb2, HasThumb2DSP]>;
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} // neverHasSideEffects
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// Rounding variants of the below included for disassembly only
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@ -2233,7 +2242,8 @@ def t2UMAAL : T2MulLong<0b110, 0b0110,
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// Most significant word multiply
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def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
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"smmul", "\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]> {
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[(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b101;
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@ -2242,7 +2252,8 @@ def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
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}
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def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
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"smmulr", "\t$Rd, $Rn, $Rm", []> {
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"smmulr", "\t$Rd, $Rn, $Rm", []>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b101;
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@ -2253,7 +2264,8 @@ def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
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def t2SMMLA : T2FourReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
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"smmla", "\t$Rd, $Rn, $Rm, $Ra",
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[(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]> {
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[(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b101;
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@ -2262,7 +2274,8 @@ def t2SMMLA : T2FourReg<
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def t2SMMLAR: T2FourReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
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"smmlar", "\t$Rd, $Rn, $Rm, $Ra", []> {
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"smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b101;
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@ -2272,7 +2285,8 @@ def t2SMMLAR: T2FourReg<
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def t2SMMLS: T2FourReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
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"smmls", "\t$Rd, $Rn, $Rm, $Ra",
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[(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]> {
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[(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b110;
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@ -2281,7 +2295,8 @@ def t2SMMLS: T2FourReg<
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def t2SMMLSR:T2FourReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
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"smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []> {
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"smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b110;
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@ -2292,7 +2307,8 @@ multiclass T2I_smul<string opc, PatFrag opnode> {
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def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
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!strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
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(sext_inreg rGPR:$Rm, i16)))]> {
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(sext_inreg rGPR:$Rm, i16)))]>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b001;
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@ -2304,7 +2320,8 @@ multiclass T2I_smul<string opc, PatFrag opnode> {
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def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
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!strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
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(sra rGPR:$Rm, (i32 16))))]> {
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(sra rGPR:$Rm, (i32 16))))]>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b001;
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@ -2316,7 +2333,8 @@ multiclass T2I_smul<string opc, PatFrag opnode> {
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def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
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!strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
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(sext_inreg rGPR:$Rm, i16)))]> {
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(sext_inreg rGPR:$Rm, i16)))]>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b001;
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@ -2328,7 +2346,8 @@ multiclass T2I_smul<string opc, PatFrag opnode> {
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def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
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!strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
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(sra rGPR:$Rm, (i32 16))))]> {
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(sra rGPR:$Rm, (i32 16))))]>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b001;
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@ -2340,7 +2359,8 @@ multiclass T2I_smul<string opc, PatFrag opnode> {
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def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
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!strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
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(sext_inreg rGPR:$Rm, i16)), (i32 16)))]> {
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(sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b011;
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@ -2352,7 +2372,8 @@ multiclass T2I_smul<string opc, PatFrag opnode> {
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def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
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!strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
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(sra rGPR:$Rm, (i32 16))), (i32 16)))]> {
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(sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b011;
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@ -2369,7 +2390,8 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
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!strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
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[(set rGPR:$Rd, (add rGPR:$Ra,
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(opnode (sext_inreg rGPR:$Rn, i16),
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(sext_inreg rGPR:$Rm, i16))))]> {
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(sext_inreg rGPR:$Rm, i16))))]>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b001;
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@ -2381,7 +2403,8 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
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(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
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!strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
|
||||
(sra rGPR:$Rm, (i32 16)))))]> {
|
||||
(sra rGPR:$Rm, (i32 16)))))]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b001;
|
||||
@ -2393,7 +2416,8 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
|
||||
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
|
||||
!strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
|
||||
(sext_inreg rGPR:$Rm, i16))))]> {
|
||||
(sext_inreg rGPR:$Rm, i16))))]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b001;
|
||||
@ -2405,7 +2429,8 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
|
||||
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
|
||||
!strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
|
||||
(sra rGPR:$Rm, (i32 16)))))]> {
|
||||
(sra rGPR:$Rm, (i32 16)))))]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b001;
|
||||
@ -2417,7 +2442,8 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
|
||||
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
|
||||
!strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
|
||||
(sext_inreg rGPR:$Rm, i16)), (i32 16))))]> {
|
||||
(sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b011;
|
||||
@ -2429,7 +2455,8 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
|
||||
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
|
||||
!strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
|
||||
(sra rGPR:$Rm, (i32 16))), (i32 16))))]> {
|
||||
(sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b011;
|
||||
@ -2444,66 +2471,82 @@ defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
|
||||
// Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
|
||||
def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
|
||||
[/* For disassembly only; pattern left blank */]>;
|
||||
[/* For disassembly only; pattern left blank */]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
|
||||
[/* For disassembly only; pattern left blank */]>;
|
||||
[/* For disassembly only; pattern left blank */]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
|
||||
[/* For disassembly only; pattern left blank */]>;
|
||||
[/* For disassembly only; pattern left blank */]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
|
||||
[/* For disassembly only; pattern left blank */]>;
|
||||
[/* For disassembly only; pattern left blank */]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
|
||||
// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
|
||||
// These are for disassembly only.
|
||||
|
||||
def t2SMUAD: T2ThreeReg_mac<
|
||||
0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
|
||||
IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []> {
|
||||
IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
let Inst{15-12} = 0b1111;
|
||||
}
|
||||
def t2SMUADX:T2ThreeReg_mac<
|
||||
0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
|
||||
IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []> {
|
||||
IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
let Inst{15-12} = 0b1111;
|
||||
}
|
||||
def t2SMUSD: T2ThreeReg_mac<
|
||||
0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
|
||||
IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []> {
|
||||
IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
let Inst{15-12} = 0b1111;
|
||||
}
|
||||
def t2SMUSDX:T2ThreeReg_mac<
|
||||
0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
|
||||
IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []> {
|
||||
IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
let Inst{15-12} = 0b1111;
|
||||
}
|
||||
def t2SMLAD : T2ThreeReg_mac<
|
||||
0, 0b010, 0b0000, (outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
|
||||
"\t$Rd, $Rn, $Rm, $Ra", []>;
|
||||
"\t$Rd, $Rn, $Rm, $Ra", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
def t2SMLADX : T2FourReg_mac<
|
||||
0, 0b010, 0b0001, (outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
|
||||
"\t$Rd, $Rn, $Rm, $Ra", []>;
|
||||
"\t$Rd, $Rn, $Rm, $Ra", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
|
||||
"\t$Rd, $Rn, $Rm, $Ra", []>;
|
||||
"\t$Rd, $Rn, $Rm, $Ra", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
|
||||
"\t$Rd, $Rn, $Rm, $Ra", []>;
|
||||
"\t$Rd, $Rn, $Rm, $Ra", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
|
||||
"\t$Ra, $Rd, $Rm, $Rn", []>;
|
||||
"\t$Ra, $Rd, $Rm, $Rn", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
|
||||
"\t$Ra, $Rd, $Rm, $Rn", []>;
|
||||
"\t$Ra, $Rd, $Rm, $Rn", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
|
||||
"\t$Ra, $Rd, $Rm, $Rn", []>;
|
||||
"\t$Ra, $Rd, $Rm, $Rn", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
|
||||
"\t$Ra, $Rd, $Rm, $Rn", []>;
|
||||
"\t$Ra, $Rd, $Rm, $Rn", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Division Instructions.
|
||||
|
||||
@ -62,6 +62,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
|
||||
, HasMPExtension(false)
|
||||
, FPOnlySP(false)
|
||||
, AllowsUnalignedMem(false)
|
||||
, Thumb2DSP(false)
|
||||
, stackAlignment(4)
|
||||
, CPUString(CPU)
|
||||
, TargetTriple(TT)
|
||||
@ -98,6 +99,9 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
|
||||
if (Len >= Idx+2 && TT[Idx+1] == 'm') {
|
||||
ARMArchVersion = V7M;
|
||||
ARMArchFeature = "+v7m";
|
||||
} else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
|
||||
ARMArchVersion = V7EM;
|
||||
ARMArchFeature = "+v7em";
|
||||
}
|
||||
} else if (SubVer == '6') {
|
||||
ARMArchVersion = V6;
|
||||
|
||||
@ -28,7 +28,7 @@ class GlobalValue;
|
||||
class ARMSubtarget : public ARMGenSubtargetInfo {
|
||||
protected:
|
||||
enum ARMArchEnum {
|
||||
V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M
|
||||
V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M, V7EM
|
||||
};
|
||||
|
||||
enum ARMProcFamilyEnum {
|
||||
@ -45,7 +45,7 @@ protected:
|
||||
};
|
||||
|
||||
/// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
|
||||
/// V6, V6T2, V7A, V7M.
|
||||
/// V6, V6T2, V7A, V7M, V7EM.
|
||||
ARMArchEnum ARMArchVersion;
|
||||
|
||||
/// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
|
||||
@ -130,6 +130,10 @@ protected:
|
||||
/// ARMTargetLowering::allowsUnalignedMemoryAccesses().
|
||||
bool AllowsUnalignedMem;
|
||||
|
||||
/// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
|
||||
/// and such) instructions in Thumb2 code.
|
||||
bool Thumb2DSP;
|
||||
|
||||
/// stackAlignment - The minimum alignment known to hold of the stack frame on
|
||||
/// entry to the function and which must be maintained by every function.
|
||||
unsigned stackAlignment;
|
||||
@ -199,6 +203,7 @@ protected:
|
||||
bool prefers32BitThumb() const { return Pref32BitThumb; }
|
||||
bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
|
||||
bool hasMPExtension() const { return HasMPExtension; }
|
||||
bool hasThumb2DSP() const { return Thumb2DSP; }
|
||||
|
||||
bool hasFP16() const { return HasFP16; }
|
||||
bool hasD16() const { return HasD16; }
|
||||
|
||||
@ -1,7 +1,8 @@
|
||||
; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep smmul | count 1
|
||||
; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep umull | count 1
|
||||
; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2dsp | FileCheck %s
|
||||
|
||||
define i32 @smulhi(i32 %x, i32 %y) {
|
||||
; CHECK: smulhi
|
||||
; CHECK: smmul r0, r1, r0
|
||||
%tmp = sext i32 %x to i64 ; <i64> [#uses=1]
|
||||
%tmp1 = sext i32 %y to i64 ; <i64> [#uses=1]
|
||||
%tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
|
||||
@ -11,6 +12,8 @@ define i32 @smulhi(i32 %x, i32 %y) {
|
||||
}
|
||||
|
||||
define i32 @umulhi(i32 %x, i32 %y) {
|
||||
; CHECK: umulhi
|
||||
; CHECK: umull r1, r0, r1, r0
|
||||
%tmp = zext i32 %x to i64 ; <i64> [#uses=1]
|
||||
%tmp1 = zext i32 %y to i64 ; <i64> [#uses=1]
|
||||
%tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s
|
||||
; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk,+t2dsp | FileCheck %s
|
||||
|
||||
define i32 @f3(i32 %a, i16 %x, i32 %y) {
|
||||
; CHECK: f3
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s
|
||||
; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk,+t2dsp | FileCheck %s
|
||||
|
||||
@x = weak global i16 0 ; <i16*> [#uses=1]
|
||||
@y = weak global i16 0 ; <i16*> [#uses=0]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user