From a768a4954818456fa6fe2077a3cbe75979025c15 Mon Sep 17 00:00:00 2001
From: Amaury de la Vieuville <amaury.dlv@gmail.com>
Date: Fri, 14 Jun 2013 11:21:35 +0000
Subject: [PATCH] ARM: fix thumb coprocessor instruction with pre-writeback
 disassembly

was        stc2 p0, c0, [r0]!
instead of stc2 p0, c0, [r0,#0]!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183975 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMInstrThumb2.td         | 2 +-
 test/MC/Disassembler/ARM/thumb-tests.txt | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index ff21bf70ecd..8b114a83264 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -3632,7 +3632,7 @@ multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
     let DecoderMethod = "DecodeCopMemInstruction";
   }
   def _PRE : T2CI<op31_28,
-                  (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
+                  (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
                   asm, "\t$cop, $CRd, $addr!"> {
     bits<13> addr;
     bits<4> cop;
diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt
index 757ce6e3977..84dd0753a69 100644
--- a/test/MC/Disassembler/ARM/thumb-tests.txt
+++ b/test/MC/Disassembler/ARM/thumb-tests.txt
@@ -221,6 +221,9 @@
 # CHECK:	stc2	p12, c15, [r9], {137}
 0x89 0xfc 0x89 0xfc
 
+# CHECK:	stc2	p0, c0, [r0, #0]!
+0xa0 0xfd 0x00 0x00
+
 # CHECK:	vmov	r1, r0, d11
 0x50 0xec 0x1b 0x1b