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We don't really care about correct register liveness information after the

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post-ra scheduler has run. Disable the verifier checks that late in the game.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97837 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-03-05 21:49:13 +00:00
parent 580bba2b0d
commit a76e816844
2 changed files with 59 additions and 4 deletions
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14
lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -212,6 +212,12 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
return false; // success!
}
static void printNoVerify(PassManagerBase &PM,
const char *Banner) {
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
}
static void printAndVerify(PassManagerBase &PM,
const char *Banner,
bool allowDoubleDefs = false) {
@ -378,13 +384,13 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
// Branch folding must be run after regalloc and prolog/epilog insertion.
if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
printAndVerify(PM, "After BranchFolding");
printNoVerify(PM, "After BranchFolding");
}
// Tail duplication.
if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
PM.add(createTailDuplicatePass(false));
printAndVerify(PM, "After TailDuplicate");
printNoVerify(PM, "After TailDuplicate");
}
PM.add(createGCMachineCodeAnalysisPass());
@ -394,11 +400,11 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
PM.add(createCodePlacementOptPass());
printAndVerify(PM, "After CodePlacementOpt");
printNoVerify(PM, "After CodePlacementOpt");
}
if (addPreEmitPass(PM, OptLevel))
printAndVerify(PM, "After PreEmit passes");
printNoVerify(PM, "After PreEmit passes");
return false;
}

49
test/CodeGen/X86/2010-03-05-EFLAGS-Redef.ll Normal file
View File

@ -0,0 +1,49 @@
; RUN: llc < %s -verify-machineinstrs
;
; This test case is transformed into a single basic block by the machine
; branch folding pass. That makes a complete mess of the %EFLAGS liveness, but
; we don't care about liveness this late anyway.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin10.2"
define i32 @main(i32 %argc, i8** nocapture %argv) ssp {
entry:
br i1 undef, label %bb, label %bb2
bb: ; preds = %entry
br label %bb2
bb2: ; preds = %bb, %entry
br i1 undef, label %bb3, label %bb5
bb3: ; preds = %bb2
br label %bb5
bb5: ; preds = %bb3, %bb2
br i1 undef, label %bb.nph239, label %bb8
bb.nph239: ; preds = %bb5
unreachable
bb8: ; preds = %bb5
br i1 undef, label %bb.nph237, label %bb47
bb.nph237: ; preds = %bb8
unreachable
bb47: ; preds = %bb8
br i1 undef, label %bb49, label %bb48
bb48: ; preds = %bb47
unreachable
bb49: ; preds = %bb47
br i1 undef, label %bb51, label %bb50
bb50: ; preds = %bb49
ret i32 0
bb51: ; preds = %bb49
ret i32 0
}