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Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the

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instruction set has no 64-bit SRA support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141570 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem 2011-10-10 19:31:45 +00:00
parent 9ac743a4ee
commit a7934dd8e4
2 changed files with 7 additions and 15 deletions
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14
lib/Target/X86/X86ISelLowering.cpp
View File

@ -10125,11 +10125,6 @@ SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG)
switch (VT.getSimpleVT().SimpleTy) {
default:
return SDValue();
case MVT::v2i64: {
SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q;
SRAIntrinsicsID = 0;
break;
}
case MVT::v4i32: {
SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
@ -10149,12 +10144,9 @@ SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG)
// In case of 1 bit sext, no need to shr
if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1;
if (SRAIntrinsicsID) {
Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(SRAIntrinsicsID, MVT::i32),
Tmp1, ShAmt);
}
return Tmp1;
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(SRAIntrinsicsID, MVT::i32),
Tmp1, ShAmt);
}
return SDValue();

8
test/CodeGen/X86/sse2-blend.ll
View File

@ -24,8 +24,8 @@ define void@vsel_i32(<4 x i32>* %v1, <4 x i32>* %v2) {
; CHECK: vsel_i64
; CHECK: pxor
; CHECK: pand
; CHECK: pandn
; CHECK: por
; CHECK: andnps
; CHECK: orps
; CHECK: ret
define void@vsel_i64(<4 x i64>* %v1, <4 x i64>* %v2) {
@ -39,8 +39,8 @@ define void@vsel_i64(<4 x i64>* %v1, <4 x i64>* %v2) {
; CHECK: vsel_double
; CHECK: pxor
; CHECK: pand
; CHECK: pandn
; CHECK: por
; CHECK: andnps
; CHECK: orps
; CHECK: ret