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Yet more ARM NEON assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142416 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1976,8 +1976,8 @@ class N3VQSL<bits<2> op21_20, bits<4> op11_8,
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InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, SDNode ShOp>
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: N3VLane32<1, 1, op21_20, op11_8, 1, 0,
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(outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
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NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
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(outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
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NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
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[(set (ResTy QPR:$Vd),
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(ResTy (ShOp (ResTy QPR:$Vn),
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(ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
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@ -1987,8 +1987,8 @@ class N3VQSL<bits<2> op21_20, bits<4> op11_8,
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class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, SDNode ShOp>
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: N3VLane16<1, 1, op21_20, op11_8, 1, 0,
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(outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
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NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
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(outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
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NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
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[(set (ResTy QPR:$Vd),
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(ResTy (ShOp (ResTy QPR:$Vn),
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(ResTy (NEONvduplane (OpTy DPR_8:$Vm),
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@ -2050,8 +2050,8 @@ class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
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string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
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: N3VLane32<1, 1, op21_20, op11_8, 1, 0,
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(outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
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NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
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(outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
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NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
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[(set (ResTy QPR:$Vd),
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(ResTy (IntOp (ResTy QPR:$Vn),
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(ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
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@ -2062,8 +2062,8 @@ class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
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string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
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: N3VLane16<1, 1, op21_20, op11_8, 1, 0,
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(outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
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NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
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(outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
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NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
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[(set (ResTy QPR:$Vd),
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(ResTy (IntOp (ResTy QPR:$Vn),
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(ResTy (NEONvduplane (OpTy DPR_8:$Vm),
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@ -2252,9 +2252,9 @@ class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
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ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
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: N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
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(outs QPR:$Vd),
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(ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
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(ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
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NVMulSLFrm, itin,
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OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
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OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
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[(set (ResTy QPR:$Vd),
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(ResTy (IntOp (ResTy QPR:$src1),
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(OpTy DPR:$Vn),
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@ -2299,8 +2299,8 @@ class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
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InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType TyQ, ValueType TyD, SDNode OpNode>
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: N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
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(outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
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NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
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(outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
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NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
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[(set QPR:$Vd,
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(TyQ (OpNode (TyD DPR:$Vn),
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(TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
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@ -2308,8 +2308,8 @@ class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
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InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType TyQ, ValueType TyD, SDNode OpNode>
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: N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
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(outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
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NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
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(outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
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NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
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[(set QPR:$Vd,
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(TyQ (OpNode (TyD DPR:$Vn),
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(TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
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@ -2354,8 +2354,8 @@ class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
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string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
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: N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
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(outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
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NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
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(outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
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NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
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[(set (ResTy QPR:$Vd),
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(ResTy (IntOp (OpTy DPR:$Vn),
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(OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
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@ -2364,8 +2364,8 @@ class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
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InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
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: N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
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(outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
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NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
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(outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
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NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
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[(set (ResTy QPR:$Vd),
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(ResTy (IntOp (OpTy DPR:$Vn),
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(OpTy (NEONvduplane (OpTy DPR_8:$Vm),
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