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teach SimplifyDemandedBits that exact shifts demand the bits they

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are shifting out since they do require them to be zeros.  Similarly
for NUW/NSW bits of shl


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125263 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2011-02-10 05:09:34 +00:00
parent 4d96c638af
commit a81556fb52
1 changed files with 23 additions and 3 deletions
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26
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
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@ -576,8 +576,16 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
break; break;
case Instruction::Shl: case Instruction::Shl:
if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) { if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
uint64_t ShiftAmt = SA->getLimitedValue(BitWidth); uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt)); APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
// If the shift is NUW/NSW, then it does demand the high bits.
ShlOperator *IOp = cast<ShlOperator>(I);
if (IOp->hasNoSignedWrap())
DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
else if (IOp->hasNoUnsignedWrap())
DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn, if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn,
KnownZero, KnownOne, Depth+1)) KnownZero, KnownOne, Depth+1))
return I; return I;
@ -592,10 +600,16 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
case Instruction::LShr: case Instruction::LShr:
// For a logical shift right // For a logical shift right
if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) { if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
uint64_t ShiftAmt = SA->getLimitedValue(BitWidth); uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
// Unsigned shift right. // Unsigned shift right.
APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt)); APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
// If the shift is exact, then it does demand the low bits (and knows that
// they are zero).
if (cast<LShrOperator>(I)->isExact())
DemandedMaskIn |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn, if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn,
KnownZero, KnownOne, Depth+1)) KnownZero, KnownOne, Depth+1))
return I; return I;
@ -627,7 +641,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
return I->getOperand(0); return I->getOperand(0);
if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) { if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
uint32_t ShiftAmt = SA->getLimitedValue(BitWidth); uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
// Signed shift right. // Signed shift right.
APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt)); APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
@ -635,6 +649,12 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// demanded. // demanded.
if (DemandedMask.countLeadingZeros() <= ShiftAmt) if (DemandedMask.countLeadingZeros() <= ShiftAmt)
DemandedMaskIn.setBit(BitWidth-1); DemandedMaskIn.setBit(BitWidth-1);
// If the shift is exact, then it does demand the low bits (and knows that
// they are zero).
if (cast<AShrOperator>(I)->isExact())
DemandedMaskIn |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn, if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn,
KnownZero, KnownOne, Depth+1)) KnownZero, KnownOne, Depth+1))
return I; return I;