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Support fp64 immediate zero, this fixes only part of PR5445

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because the testcase is triggering one more bug.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88674 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
2009-11-13 18:49:59 +00:00
parent 01205a80f5
commit a8173b934f
2 changed files with 22 additions and 3 deletions
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15
lib/Target/Mips/MipsInstrInfo.cpp
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@@ -134,6 +134,9 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
DebugLoc DL = DebugLoc::getUnknownLoc();
const MachineFunction *MF = MBB.getParent();
const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
if (I != MBB.end()) DL = I->getDebugLoc();
if (DestRC != SrcRC) {
@@ -153,6 +156,13 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
else if ((DestRC == Mips::FGR32RegisterClass) &&
(SrcRC == Mips::CPURegsRegisterClass))
BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
else if ((DestRC == Mips::AFGR64RegisterClass) &&
(SrcRC == Mips::CPURegsRegisterClass) &&
(SrcReg == Mips::ZERO)) {
const unsigned *AliasSet = TRI->getAliasSet(DestReg);
BuildMI(MBB, I, DL, get(Mips::MTC1), AliasSet[0]).addReg(SrcReg);
BuildMI(MBB, I, DL, get(Mips::MTC1), AliasSet[1]).addReg(SrcReg);
}
// Move from/to Hi/Lo registers
else if ((DestRC == Mips::HILORegisterClass) &&
@@ -163,9 +173,8 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
(DestRC == Mips::CPURegsRegisterClass)) {
unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
BuildMI(MBB, I, DL, get(Opc), DestReg);
// Can't copy this register
} else
} else
// Can't copy this register
return false;
return true;