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PR9998: ashr exact %x, 31 is not equivalent to sdiv exact %x, -2147483648.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132097 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -919,11 +919,11 @@ Instruction *InstCombiner::FoldICmpShrCst(ICmpInst &ICI, BinaryOperator *Shr,
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if (ICI.isSigned() != (Shr->getOpcode() == Instruction::AShr))
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if (ICI.isSigned() != (Shr->getOpcode() == Instruction::AShr))
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return 0;
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return 0;
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// Otherwise, all lshr and all exact ashr's are equivalent to a udiv/sdiv by
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// Otherwise, all lshr and most exact ashr's are equivalent to a udiv/sdiv
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// a power of 2. Since we already have logic to simplify these, transform
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// by a power of 2. Since we already have logic to simplify these,
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// to div and then simplify the resultant comparison.
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// transform to div and then simplify the resultant comparison.
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if (Shr->getOpcode() == Instruction::AShr &&
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if (Shr->getOpcode() == Instruction::AShr &&
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!Shr->isExact())
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(!Shr->isExact() || ShAmtVal == TypeBits - 1))
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return 0;
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return 0;
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// Revisit the shift (to delete it).
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// Revisit the shift (to delete it).
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@ -96,6 +96,22 @@ define i1 @ashr_icmp2(i64 %X) nounwind {
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ret i1 %Z
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ret i1 %Z
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}
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}
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; PR9998
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; Make sure we don't transform the ashr here into an sdiv
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; CHECK: @pr9998
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; CHECK: = and i32 %V, 1
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; CHECK: %Z = icmp ne
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; CHECK: ret i1 %Z
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define i1 @pr9998(i32 %V) nounwind {
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entry:
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%W = shl i32 %V, 31
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%X = ashr exact i32 %W, 31
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%Y = sext i32 %X to i64
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%Z = icmp ugt i64 %Y, 7297771788697658747
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ret i1 %Z
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}
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; CHECK: @udiv_icmp1
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; CHECK: @udiv_icmp1
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; CHECK: icmp ne i64 %X, 0
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; CHECK: icmp ne i64 %X, 0
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define i1 @udiv_icmp1(i64 %X) nounwind {
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define i1 @udiv_icmp1(i64 %X) nounwind {
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