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PR9998: ashr exact %x, 31 is not equivalent to sdiv exact %x, -2147483648.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132097 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2011-05-25 23:26:20 +00:00
parent 8a115d5bf4
commit a831a9b972
2 changed files with 20 additions and 4 deletions
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8
lib/Transforms/InstCombine/InstCombineCompares.cpp
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@ -919,11 +919,11 @@ Instruction *InstCombiner::FoldICmpShrCst(ICmpInst &ICI, BinaryOperator *Shr,
if (ICI.isSigned() != (Shr->getOpcode() == Instruction::AShr)) if (ICI.isSigned() != (Shr->getOpcode() == Instruction::AShr))
return 0; return 0;
// Otherwise, all lshr and all exact ashr's are equivalent to a udiv/sdiv by // Otherwise, all lshr and most exact ashr's are equivalent to a udiv/sdiv
// a power of 2. Since we already have logic to simplify these, transform // by a power of 2. Since we already have logic to simplify these,
// to div and then simplify the resultant comparison. // transform to div and then simplify the resultant comparison.
if (Shr->getOpcode() == Instruction::AShr && if (Shr->getOpcode() == Instruction::AShr &&
!Shr->isExact()) (!Shr->isExact() || ShAmtVal == TypeBits - 1))
return 0; return 0;
// Revisit the shift (to delete it). // Revisit the shift (to delete it).

16
test/Transforms/InstCombine/exact.ll
View File

@ -96,6 +96,22 @@ define i1 @ashr_icmp2(i64 %X) nounwind {
ret i1 %Z ret i1 %Z
} }
; PR9998
; Make sure we don't transform the ashr here into an sdiv
; CHECK: @pr9998
; CHECK: = and i32 %V, 1
; CHECK: %Z = icmp ne
; CHECK: ret i1 %Z
define i1 @pr9998(i32 %V) nounwind {
entry:
%W = shl i32 %V, 31
%X = ashr exact i32 %W, 31
%Y = sext i32 %X to i64
%Z = icmp ugt i64 %Y, 7297771788697658747
ret i1 %Z
}
; CHECK: @udiv_icmp1 ; CHECK: @udiv_icmp1
; CHECK: icmp ne i64 %X, 0 ; CHECK: icmp ne i64 %X, 0
define i1 @udiv_icmp1(i64 %X) nounwind { define i1 @udiv_icmp1(i64 %X) nounwind {