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This patch addresses a problem with the Post RA scheduler generating an

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incorrect instruction sequence due to it not being aware that an
inline assembly instruction may reference memory.

This patch fixes the problem by causing the scheduler to always assume that any
inline assembly code instruction could access memory. This is necessary because
the internal representation of the inline instruction does not include
any information about memory accesses.
 
This should fix PR13504.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166929 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Preston Gurd
2012-10-29 15:01:23 +00:00
parent 01d013ec04
commit a836563e32
2 changed files with 18 additions and 0 deletions
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13
test/CodeGen/X86/inlineasm-sched-bug.ll Normal file
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; PR13504
; RUN: llc -march=x86 -mcpu=atom <%s | FileCheck %s
; CHECK: bsfl
; CHECK-NOT: movl
define i32 @foo(i32 %treemap) nounwind uwtable {
entry:
%sub = sub i32 0, %treemap
%and = and i32 %treemap, %sub
%0 = tail call i32 asm "bsfl $1,$0\0A\09", "=r,rm,~{dirflag},~{fpsr},~{flags}"(i32 %and) nounwind
ret i32 %0
}