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Compile this:
short test4(unsigned X) { return (X >> 16); } to: _test4: movl 4(%esp), %eax sarl $16, %eax ret instead of: _test4: movl $-65536, %eax andl 4(%esp), %eax sarl $16, %eax ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28171 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1575,6 +1575,11 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
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}
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}
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// Simplify, based on bits shifted out of the LHS.
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if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
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return SDOperand(N, 0);
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// If the sign bit is known to be zero, switch this to a SRL.
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if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
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return DAG.getNode(ISD::SRL, VT, N0, N1);
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