mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171117 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
8c6cb31f6e
commit
a85cbfeba7
@ -203,9 +203,8 @@ multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
|
||||
string OpcodeStr, X86MemOperand x86memop,
|
||||
list<dag> pat_rr, list<dag> pat_rm,
|
||||
bit Is2Addr = 1,
|
||||
bit rr_hasSideEffects = 0> {
|
||||
let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
|
||||
bit Is2Addr = 1> {
|
||||
let isCommutable = 1, hasSideEffects = 0 in
|
||||
def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
|
||||
!if(Is2Addr,
|
||||
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
||||
@ -2766,7 +2765,7 @@ multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
|
||||
defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
|
||||
!strconcat(OpcodeStr, "ps"), f128mem, [],
|
||||
[(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
|
||||
(memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
|
||||
(memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
|
||||
|
||||
defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
|
||||
!strconcat(OpcodeStr, "pd"), f128mem,
|
||||
|
Loading…
Reference in New Issue
Block a user