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X86: Add patterns for the movbe instruction (mov + bswap, only available on atom)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141563 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2,11 +2,6 @@
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// Random ideas for the X86 backend.
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//===---------------------------------------------------------------------===//
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We should add support for the "movbe" instruction, which does a byte-swapping
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copy (3-addr bswap + memory support?) This is available on Atom processors.
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//===---------------------------------------------------------------------===//
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This should be one DIV/IDIV instruction, not a libcall:
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unsigned test(unsigned long long X, unsigned Y) {
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@ -133,7 +133,7 @@ def : Proc<"core2", [FeatureSSSE3, FeatureCMPXCHG16B,
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FeatureSlowBTMem]>;
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def : Proc<"penryn", [FeatureSSE41, FeatureCMPXCHG16B,
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FeatureSlowBTMem]>;
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def : Proc<"atom", [FeatureSSE3, FeatureCMPXCHG16B,
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def : Proc<"atom", [FeatureSSE3, FeatureCMPXCHG16B, FeatureMOVBE,
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FeatureSlowBTMem]>;
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// "Arrandale" along with corei3 and corei5
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def : Proc<"corei7", [FeatureSSE42, FeatureCMPXCHG16B,
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@ -1308,17 +1308,23 @@ def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
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//
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let Predicates = [HasMOVBE] in {
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def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"movbe{w}\t{$src, $dst|$dst, $src}", []>, OpSize, T8;
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"movbe{w}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, OpSize, T8;
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def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"movbe{l}\t{$src, $dst|$dst, $src}", []>, T8;
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"movbe{l}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, T8;
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def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"movbe{q}\t{$src, $dst|$dst, $src}", []>, T8;
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"movbe{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, T8;
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def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
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"movbe{w}\t{$src, $dst|$dst, $src}", []>, OpSize, T8;
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"movbe{w}\t{$src, $dst|$dst, $src}",
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[(store (bswap GR16:$src), addr:$dst)]>, OpSize, T8;
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def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
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"movbe{l}\t{$src, $dst|$dst, $src}", []>, T8;
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"movbe{l}\t{$src, $dst|$dst, $src}",
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[(store (bswap GR32:$src), addr:$dst)]>, T8;
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def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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"movbe{q}\t{$src, $dst|$dst, $src}", []>, T8;
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"movbe{q}\t{$src, $dst|$dst, $src}",
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[(store (bswap GR64:$src), addr:$dst)]>, T8;
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}
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//===----------------------------------------------------------------------===//
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36
test/CodeGen/X86/movbe.ll
Normal file
36
test/CodeGen/X86/movbe.ll
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@ -0,0 +1,36 @@
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; RUN: llc -march=x86-64 -mcpu=atom < %s | FileCheck %s
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declare i32 @llvm.bswap.i32(i32) nounwind readnone
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declare i64 @llvm.bswap.i64(i64) nounwind readnone
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define void @test1(i32* nocapture %x, i32 %y) nounwind {
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%bswap = call i32 @llvm.bswap.i32(i32 %y)
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store i32 %bswap, i32* %x, align 4
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ret void
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; CHECK: test1:
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; CHECK: movbel %esi, (%rdi)
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}
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define i32 @test2(i32* %x) nounwind {
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%load = load i32* %x, align 4
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%bswap = call i32 @llvm.bswap.i32(i32 %load)
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ret i32 %bswap
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; CHECK: test2:
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; CHECK: movbel (%rdi), %eax
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}
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define void @test3(i64* %x, i64 %y) nounwind {
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%bswap = call i64 @llvm.bswap.i64(i64 %y)
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store i64 %bswap, i64* %x, align 8
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ret void
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; CHECK: test3:
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; CHECK: movbeq %rsi, (%rdi)
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}
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define i64 @test4(i64* %x) nounwind {
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%load = load i64* %x, align 8
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%bswap = call i64 @llvm.bswap.i64(i64 %load)
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ret i64 %bswap
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; CHECK: test4:
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; CHECK: movbeq (%rdi), %rax
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}
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