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Add NEON encodings for vmov and vmvn of immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117374 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
parent
e459d55f28
commit
a88ea03bf2
@ -1683,6 +1683,16 @@ class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
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let Inst{6} = op6;
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let Inst{5} = op5;
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let Inst{4} = op4;
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// Instruction operands.
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bits<5> Vd;
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bits<13> SIMM;
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let Inst{15-12} = Vd{3-0};
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let Inst{22} = Vd{4};
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let Inst{24} = SIMM{7};
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let Inst{18-16} = SIMM{6-4};
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let Inst{3-0} = SIMM{3-0};
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}
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// NEON 2 vector register format.
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@ -2899,26 +2899,34 @@ def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
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// VMVN : Vector Bitwise NOT (Immediate)
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let isReMaterializable = 1 in {
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// FIXME: This instruction's encoding MAY NOT BE correct.
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def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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"vmvn", "i16", "$dst, $SIMM", "",
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[(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]>;
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// FIXME: This instruction's encoding MAY NOT BE correct.
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[(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
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let Inst{9} = SIMM{9};
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}
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def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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"vmvn", "i16", "$dst, $SIMM", "",
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[(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]>;
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// FIXME: This instruction's encoding MAY NOT BE correct.
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[(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
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let Inst{9} = SIMM{9};
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}
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def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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"vmvn", "i32", "$dst, $SIMM", "",
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[(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]>;
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// FIXME: This instruction's encoding MAY NOT BE correct.
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[(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
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let Inst{11-8} = SIMM{11-8};
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}
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def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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"vmvn", "i32", "$dst, $SIMM", "",
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[(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]>;
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[(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
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let Inst{11-8} = SIMM{11-8};
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}
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}
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// VMVN : Vector Bitwise NOT
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@ -3387,20 +3395,30 @@ def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
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def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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"vmov", "i16", "$dst, $SIMM", "",
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[(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]>;
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[(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
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let Inst{9} = SIMM{9};
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}
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def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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"vmov", "i16", "$dst, $SIMM", "",
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[(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]>;
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[(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
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let Inst{9} = SIMM{9};
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}
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def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$dst),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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"vmov", "i32", "$dst, $SIMM", "",
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[(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]>;
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[(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
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let Inst{11-8} = SIMM{11-8};
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}
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def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$dst),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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"vmov", "i32", "$dst, $SIMM", "",
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[(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]>;
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[(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
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let Inst{11-8} = SIMM{11-8};
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}
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def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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@ -2,7 +2,6 @@
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; FIXME: The following instructions still require testing:
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; - vand with immediate, vorr with immediate
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; - vmvn of an immediate
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; - both vbit and vbif
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; CHECK: vand_8xi8
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169
test/MC/ARM/neon-mov-encoding.ll
Normal file
169
test/MC/ARM/neon-mov-encoding.ll
Normal file
@ -0,0 +1,169 @@
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; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
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; CHECK: vmov_8xi8
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define <8 x i8> @vmov_8xi8() nounwind {
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; CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2]
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ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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}
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; CHECK: vmov_4xi16a
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define <4 x i16> @vmov_4xi16a() nounwind {
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; CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2]
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ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
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}
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; CHECK: vmov_4xi16b
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define <4 x i16> @vmov_4xi16b() nounwind {
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; CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2]
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ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
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}
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; CHECK: vmov_2xi32a
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define <2 x i32> @vmov_2xi32a() nounwind {
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; CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2]
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ret <2 x i32> < i32 32, i32 32 >
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}
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; CHECK: vmov_2xi32b
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define <2 x i32> @vmov_2xi32b() nounwind {
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; CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2]
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ret <2 x i32> < i32 8192, i32 8192 >
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}
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; CHECK: vmov_2xi32c
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define <2 x i32> @vmov_2xi32c() nounwind {
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; CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2]
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ret <2 x i32> < i32 2097152, i32 2097152 >
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}
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; CHECK: vmov_2xi32d
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define <2 x i32> @vmov_2xi32d() nounwind {
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; CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2]
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ret <2 x i32> < i32 536870912, i32 536870912 >
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}
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; CHECK: vmov_2xi32e
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define <2 x i32> @vmov_2xi32e() nounwind {
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; CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2]
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ret <2 x i32> < i32 8447, i32 8447 >
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}
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; CHECK: vmov_2xi32f
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define <2 x i32> @vmov_2xi32f() nounwind {
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; CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2]
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ret <2 x i32> < i32 2162687, i32 2162687 >
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}
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; CHECK: vmov_1xi64
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define <1 x i64> @vmov_1xi64() nounwind {
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; CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3]
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ret <1 x i64> < i64 18374687574888349695 >
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}
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; CHECK: vmov_16xi8
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define <16 x i8> @vmov_16xi8() nounwind {
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; CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2]
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ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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}
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; CHECK: vmov_8xi16a
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define <8 x i16> @vmov_8xi16a() nounwind {
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; CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2]
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ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
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}
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; CHECK: vmov_8xi16b
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define <8 x i16> @vmov_8xi16b() nounwind {
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; CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2]
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ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
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}
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; CHECK: vmov_4xi32a
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define <4 x i32> @vmov_4xi32a() nounwind {
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; CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2]
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ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
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}
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; CHECK: vmov_4xi32b
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define <4 x i32> @vmov_4xi32b() nounwind {
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; CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2]
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ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
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}
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; CHECK: vmov_4xi32c
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define <4 x i32> @vmov_4xi32c() nounwind {
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; CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2]
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ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
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}
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; CHECK: vmov_4xi32d
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define <4 x i32> @vmov_4xi32d() nounwind {
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; CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2]
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ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
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}
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; CHECK: vmov_4xi32e
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define <4 x i32> @vmov_4xi32e() nounwind {
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; CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2]
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ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
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}
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; CHECK: vmov_4xi32f
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define <4 x i32> @vmov_4xi32f() nounwind {
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; CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2]
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ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
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}
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; CHECK: vmov_2xi64
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define <2 x i64> @vmov_2xi64() nounwind {
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; CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3]
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ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
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}
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; CHECK: vmvn_4xi16a
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define <4 x i16> @vmvn_4xi16a() nounwind {
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; CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2]
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ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
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}
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; CHECK: vmvn_4xi16b
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define <4 x i16> @vmvn_4xi16b() nounwind {
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; CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2]
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ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
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}
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; CHECK: vmvn_2xi32a
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define <2 x i32> @vmvn_2xi32a() nounwind {
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; CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2]
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ret <2 x i32> < i32 4294967263, i32 4294967263 >
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}
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; CHECK: vmvn_2xi32b
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define <2 x i32> @vmvn_2xi32b() nounwind {
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; CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2]
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ret <2 x i32> < i32 4294959103, i32 4294959103 >
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}
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; CHECK: vmvn_2xi32c
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define <2 x i32> @vmvn_2xi32c() nounwind {
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; CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2]
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ret <2 x i32> < i32 4292870143, i32 4292870143 >
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}
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; CHECK: vmvn_2xi32d
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define <2 x i32> @vmvn_2xi32d() nounwind {
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; CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2]
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ret <2 x i32> < i32 3758096383, i32 3758096383 >
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}
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; CHECK: vmvn_2xi32e
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define <2 x i32> @vmvn_2xi32e() nounwind {
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; CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2]
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ret <2 x i32> < i32 4294958848, i32 4294958848 >
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}
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; CHECK: vmvn_2xi32f
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define <2 x i32> @vmvn_2xi32f() nounwind {
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; CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2]
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ret <2 x i32> < i32 4292804608, i32 4292804608 >
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}
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