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Change long binary encodings to use hex instead. It's more readable. Also

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initialize missing bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119849 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-11-19 22:02:18 +00:00
parent 76eb5f2401
commit a898166d38
1 changed files with 20 additions and 17 deletions
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37
lib/Target/ARM/ARMInstrThumb.td
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@ -126,74 +126,77 @@ def t_addrmode_sp : Operand<i32>,
// these will always be in pairs, and asserts if it finds otherwise. Better way? // these will always be in pairs, and asserts if it finds otherwise. Better way?
let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
def tADJCALLSTACKUP : def tADJCALLSTACKUP :
PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
[(ARMcallseq_end imm:$amt1, imm:$amt2)]>, [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
Requires<[IsThumb, IsThumb1Only]>; Requires<[IsThumb, IsThumb1Only]>;
def tADJCALLSTACKDOWN : def tADJCALLSTACKDOWN :
PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
[(ARMcallseq_start imm:$amt)]>, [(ARMcallseq_start imm:$amt)]>,
Requires<[IsThumb, IsThumb1Only]>; Requires<[IsThumb, IsThumb1Only]>;
} }
def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
[/* For disassembly only; pattern left blank */]>, [/* For disassembly only; pattern left blank */]>,
T1Encoding<0b101111> { T1Encoding<0b101111> {
let Inst{9-8} = 0b11; let Inst{9-8} = 0b11;
let Inst{7-0} = 0b00000000; let Inst{7-0} = 0x00;
} }
def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
[/* For disassembly only; pattern left blank */]>, [/* For disassembly only; pattern left blank */]>,
T1Encoding<0b101111> { T1Encoding<0b101111> {
let Inst{9-8} = 0b11; let Inst{9-8} = 0b11;
let Inst{7-0} = 0b00010000; let Inst{7-0} = 0x10;
} }
def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
[/* For disassembly only; pattern left blank */]>, [/* For disassembly only; pattern left blank */]>,
T1Encoding<0b101111> { T1Encoding<0b101111> {
let Inst{9-8} = 0b11; let Inst{9-8} = 0b11;
let Inst{7-0} = 0b00100000; let Inst{7-0} = 0x20;
} }
def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
[/* For disassembly only; pattern left blank */]>, [/* For disassembly only; pattern left blank */]>,
T1Encoding<0b101111> { T1Encoding<0b101111> {
let Inst{9-8} = 0b11; let Inst{9-8} = 0b11;
let Inst{7-0} = 0b00110000; let Inst{7-0} = 0x30;
} }
def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
[/* For disassembly only; pattern left blank */]>, [/* For disassembly only; pattern left blank */]>,
T1Encoding<0b101111> { T1Encoding<0b101111> {
let Inst{9-8} = 0b11; let Inst{9-8} = 0b11;
let Inst{7-0} = 0b01000000; let Inst{7-0} = 0x40;
} }
def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe", def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
[/* For disassembly only; pattern left blank */]>, [/* For disassembly only; pattern left blank */]>,
T1Encoding<0b101101> { T1Encoding<0b101101> {
let Inst{9-5} = 0b10010; let Inst{9-5} = 0b10010;
let Inst{3} = 1; let Inst{4} = 1;
let Inst{3} = 1; // Big-Endian
let Inst{2-0} = 0b000;
} }
def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle", def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
[/* For disassembly only; pattern left blank */]>, [/* For disassembly only; pattern left blank */]>,
T1Encoding<0b101101> { T1Encoding<0b101101> {
let Inst{9-5} = 0b10010; let Inst{9-5} = 0b10010;
let Inst{3} = 0; let Inst{4} = 1;
let Inst{3} = 0; // Little-Endian
let Inst{2-0} = 0b000;
} }
// The i32imm operand $val can be used by a debugger to store more information // The i32imm operand $val can be used by a debugger to store more information
// about the breakpoint. // about the breakpoint.
def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val", def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$imm8",
[/* For disassembly only; pattern left blank */]>, [/* For disassembly only; pattern left blank */]>,
T1Encoding<0b101111> { T1Encoding<0b101111> {
bits<8> val; bits<8> imm8;
let Inst{9-8} = 0b10; let Inst{9-8} = 0b10;
let Inst{7-0} = val; let Inst{7-0} = imm8;
} }
// Change Processor State is a system instruction -- for disassembly only. // Change Processor State is a system instruction -- for disassembly only.