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https://github.com/c64scene-ar/llvm-6502.git
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Define classes for FP unary instructions and multiclasses for FP-to-fixed point
conversion instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141473 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
861a410cb6
commit
a8de1c1be0
@ -73,32 +73,29 @@ def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
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// Only S32 and D32 are supported right now.
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//===----------------------------------------------------------------------===//
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multiclass FFR1_1<bits<6> funct, string asmstr>
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{
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def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
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!strconcat(asmstr, ".s\t$fd, $fs"), []>;
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// Instructions that convert an FP value to 32-bit fixed point.
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multiclass FFR1_W_M<bits<6> funct, string opstr> {
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def _S : FFR1<funct, 16, opstr, "w.s", FGR32, FGR32>;
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def _D32 : FFR1<funct, 17, opstr, "w.d", FGR32, AFGR64>,
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Requires<[NotFP64bit]>;
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def _D64 : FFR1<funct, 17, opstr, "w.d", FGR32, FGR64>,
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Requires<[IsFP64bit]>;
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}
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def _D32 : FFR<0x11, funct, 0x1, (outs FGR32:$fd), (ins AFGR64:$fs),
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!strconcat(asmstr, ".d\t$fd, $fs"), []>, Requires<[NotFP64bit]>;
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// Instructions that convert an FP value to 64-bit fixed point.
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let Predicates = [IsFP64bit] in
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multiclass FFR1_L_M<bits<6> funct, string opstr> {
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def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>;
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def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>;
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}
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multiclass FFR1_2<bits<6> funct, string asmstr, SDNode FOp>
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{
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def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
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!strconcat(asmstr, ".s\t$fd, $fs"),
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[(set FGR32:$fd, (FOp FGR32:$fs))]>;
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def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
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!strconcat(asmstr, ".d\t$fd, $fs"),
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[(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[NotFP64bit]>;
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def _S32 : FFR1P<funct, 16, asmstr, "s", FGR32, FGR32, FOp>;
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def _D32 : FFR1P<funct, 17, asmstr, "d", AFGR64, AFGR64, FOp>,
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Requires<[NotFP64bit]>;
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}
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class FFR1_3<bits<6> funct, bits<5> fmt, RegisterClass RcSrc,
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RegisterClass RcDst, string asmstr>:
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FFR<0x11, funct, fmt, (outs RcSrc:$fd), (ins RcDst:$fs),
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!strconcat(asmstr, "\t$fd, $fs"), []>;
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multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp, bit isComm = 0> {
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let isCommutable = isComm in {
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def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
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@ -117,51 +114,37 @@ multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp, bit isComm = 0> {
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//===----------------------------------------------------------------------===//
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// Floating Point Instructions
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//===----------------------------------------------------------------------===//
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defm ROUND_W : FFR1_W_M<0xc, "round">;
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defm ROUND_L : FFR1_L_M<0x8, "round">;
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defm TRUNC_W : FFR1_W_M<0xd, "trunc">;
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defm TRUNC_L : FFR1_L_M<0x9, "trunc">;
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defm CEIL_W : FFR1_W_M<0xe, "ceil">;
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defm CEIL_L : FFR1_L_M<0xa, "ceil">;
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defm FLOOR_W : FFR1_W_M<0xf, "floor">;
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defm FLOOR_L : FFR1_L_M<0xb, "floor">;
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defm CVT_W : FFR1_W_M<0x24, "cvt">;
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defm CVT_L : FFR1_L_M<0x25, "cvt">;
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def CVT_S_W : FFR1<0x20, 20, "cvt", "s.w", FGR32, FGR32>;
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let Predicates = [NotFP64bit] in {
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def CVT_S_D32 : FFR1<0x20, 17, "cvt", "s.d", FGR32, AFGR64>;
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def CVT_D32_W : FFR1<0x21, 20, "cvt", "d.w", AFGR64, FGR32>;
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def CVT_D32_S : FFR1<0x21, 16, "cvt", "d.s", AFGR64, FGR32>;
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}
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let Predicates = [IsFP64bit] in {
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def CVT_S_D64 : FFR1<0x20, 17, "cvt", "s.d", FGR32, FGR64>;
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def CVT_S_L : FFR1<0x20, 21, "cvt", "s.l", FGR32, FGR64>;
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def CVT_D64_W : FFR1<0x21, 20, "cvt", "d.w", FGR64, FGR32>;
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def CVT_D64_S : FFR1<0x21, 16, "cvt", "d.s", FGR64, FGR32>;
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def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>;
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}
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let ft = 0 in {
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defm FLOOR_W : FFR1_1<0b001111, "floor.w">;
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defm CEIL_W : FFR1_1<0b001110, "ceil.w">;
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defm ROUND_W : FFR1_1<0b001100, "round.w">;
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defm TRUNC_W : FFR1_1<0b001101, "trunc.w">;
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defm CVTW : FFR1_1<0b100100, "cvt.w">;
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defm FABS : FFR1_2<0b000101, "abs", fabs>;
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defm FNEG : FFR1_2<0b000111, "neg", fneg>;
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defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>;
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/// Convert to Single Precison
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def CVTS_W32 : FFR1_3<0b100000, 0x2, FGR32, FGR32, "cvt.s.w">;
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let Predicates = [IsNotSingleFloat] in {
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/// Ceil to long signed integer
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def CEIL_LS : FFR1_3<0b001010, 0x0, FGR32, FGR32, "ceil.l">;
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def CEIL_LD : FFR1_3<0b001010, 0x1, AFGR64, AFGR64, "ceil.l">;
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/// Round to long signed integer
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def ROUND_LS : FFR1_3<0b001000, 0x0, FGR32, FGR32, "round.l">;
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def ROUND_LD : FFR1_3<0b001000, 0x1, AFGR64, AFGR64, "round.l">;
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/// Floor to long signed integer
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def FLOOR_LS : FFR1_3<0b001011, 0x0, FGR32, FGR32, "floor.l">;
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def FLOOR_LD : FFR1_3<0b001011, 0x1, AFGR64, AFGR64, "floor.l">;
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/// Trunc to long signed integer
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def TRUNC_LS : FFR1_3<0b001001, 0x0, FGR32, FGR32, "trunc.l">;
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def TRUNC_LD : FFR1_3<0b001001, 0x1, AFGR64, AFGR64, "trunc.l">;
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/// Convert to long signed integer
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def CVTL_S : FFR1_3<0b100101, 0x0, FGR32, FGR32, "cvt.l">;
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def CVTL_D : FFR1_3<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">;
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/// Convert to Double Precison
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def CVTD_S32 : FFR1_3<0b100001, 0x0, AFGR64, FGR32, "cvt.d.s">;
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def CVTD_W32 : FFR1_3<0b100001, 0x2, AFGR64, FGR32, "cvt.d.w">;
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def CVTD_L32 : FFR1_3<0b100001, 0x3, AFGR64, AFGR64, "cvt.d.l">;
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/// Convert to Single Precison
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def CVTS_D32 : FFR1_3<0b100000, 0x1, FGR32, AFGR64, "cvt.s.d">;
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def CVTS_L32 : FFR1_3<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">;
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}
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}
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// The odd-numbered registers are only referenced when doing loads,
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@ -352,14 +335,14 @@ def fpimm0neg : PatLeaf<(fpimm), [{
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def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
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def : Pat<(f32 fpimm0neg), (FNEG_S32 (MTC1 ZERO))>;
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def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVTS_W32 (MTC1 CPURegs:$src))>;
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def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>;
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def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
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def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>;
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def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S32 FGR32:$src))>;
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def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
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def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
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let Predicates = [NotFP64bit] in {
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def : Pat<(f32 (fround AFGR64:$src)), (CVTS_D32 AFGR64:$src)>;
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def : Pat<(f64 (fextend FGR32:$src)), (CVTD_S32 FGR32:$src)>;
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def : Pat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
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def : Pat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
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}
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@ -226,4 +226,22 @@ class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr,
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5-0} = 17;
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}
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}
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// FP unary instructions without patterns.
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class FFR1<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
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RegisterClass DstRC, RegisterClass SrcRC> :
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FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
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!strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), []> {
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let ft = 0;
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}
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// FP unary instructions with patterns.
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class FFR1P<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
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RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> :
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FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
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!strconcat(opstr, ".", fmtstr, "\t$fd, $fs"),
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[(set DstRC:$fd, (OpNode SrcRC:$fs))]> {
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let ft = 0;
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}
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