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https://github.com/c64scene-ar/llvm-6502.git
synced 2026-04-26 12:20:42 +00:00
updated suggesting/coloring of call & return args & implicit operands.
Changed added instr to a deque (from a vector) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@831 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -108,30 +108,27 @@ void LiveRangeInfo::constructLiveRanges()
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const MachineInstr * MInst = *MInstIterator;
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// Now if the machine instruction has special operands that must be
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// set with a "suggested color", do it here.
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// This will be true for call/return instructions
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// Now if the machine instruction is a call/return instruction,
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// add it to CallRetInstrList for processing its implicit operands
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if( MRI.handleSpecialMInstr(MInst, *this, RegClassList) )
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continue;
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if( (TM.getInstrInfo()).isReturn( MInst->getOpCode()) ||
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(TM.getInstrInfo()).isCall( MInst->getOpCode()) )
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CallRetInstrList.push_back( MInst );
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// iterate over MI operands to find defs
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for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) {
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if( DEBUG_RA) {
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MachineOperand::MachineOperandType OpTyp =
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OpI.getMachineOperand().getOperandType();
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// delete later from here ************
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MachineOperand::MachineOperandType OpTyp =
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OpI.getMachineOperand().getOperandType();
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if (DEBUG_RA && OpTyp == MachineOperand::MO_CCRegister) {
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cout << "\n**CC reg found. Is Def=" << OpI.isDef() << " Val:";
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printValue( OpI.getMachineOperand().getVRegValue() );
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cout << endl;
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if ( OpTyp == MachineOperand::MO_CCRegister) {
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cout << "\n**CC reg found. Is Def=" << OpI.isDef() << " Val:";
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printValue( OpI.getMachineOperand().getVRegValue() );
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cout << endl;
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}
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}
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// ************* to here
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// create a new LR iff this operand is a def
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if( OpI.isDef() ) {
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@@ -193,52 +190,20 @@ void LiveRangeInfo::constructLiveRanges()
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}
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}
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} // if isDef()
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} // for all opereands in machine instructions
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} // for all machine instructions in the BB
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} // for all BBs in method
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// go thru LLVM instructions in the basic block and suggest colors
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// for their args. Also record all CALL
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// instructions and Return instructions in the CallRetInstrList
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// This is done because since there are no reverse pointers in machine
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// instructions to find the llvm instruction, when we encounter a call
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// or a return whose args must be specailly colored (e.g., %o's for args)
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// We have to makes sure that all LRs of call/ret args are added before
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// doing this. But return value of call will not have a LR.
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BBI = Meth->begin(); // random iterator for BBs
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// Now we have to suggest clors for call and return arg live ranges.
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// Also, if there are implicit defs (e.g., retun value of a call inst)
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// they must be added to the live range list
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for( ; BBI != Meth->end(); ++BBI) { // go thru BBs in random order
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BasicBlock::const_iterator InstIt = (*BBI)->begin();
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for( ; InstIt != (*BBI)->end() ; ++InstIt) {
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const Instruction *const CallRetI = *InstIt;
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unsigned OpCode = (CallRetI)->getOpcode();
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if( (OpCode == Instruction::Call) ) {
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CallRetInstrList.push_back(CallRetI );
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MRI.suggestRegs4CallArgs( (CallInst *) CallRetI, *this, RegClassList );
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}
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else if (OpCode == Instruction::Ret ) {
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CallRetInstrList.push_back( CallRetI );
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MRI.suggestReg4RetValue( (ReturnInst *) CallRetI, *this);
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}
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} // for each llvm instr in BB
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} // for all BBs in method
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suggestRegs4CallRets();
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if( DEBUG_RA)
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cout << "Initial Live Ranges constructed!" << endl;
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@@ -247,6 +212,34 @@ void LiveRangeInfo::constructLiveRanges()
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// Suggest colors for call and return args.
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// Also create new LRs for implicit defs
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void LiveRangeInfo::suggestRegs4CallRets()
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{
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CallRetInstrListType::const_iterator It = CallRetInstrList.begin();
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for( ; It != CallRetInstrList.end(); ++It ) {
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const MachineInstr *MInst = *It;
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MachineOpCode OpCode = MInst->getOpCode();
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if( (TM.getInstrInfo()).isReturn(OpCode) )
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MRI.suggestReg4RetValue( MInst, *this);
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else if( (TM.getInstrInfo()).isCall( OpCode ) )
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MRI.suggestRegs4CallArgs( MInst, *this, RegClassList );
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else
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assert( 0 && "Non call/ret instr in CallRetInstrList" );
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}
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}
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void LiveRangeInfo::coalesceLRs()
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{
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@@ -318,8 +311,6 @@ void LiveRangeInfo::coalesceLRs()
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if( RCOfDef == RCOfUse ) { // if the reg classes are the same
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// if( LROfUse->getTypeID() == LROfDef->getTypeID() ) {
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if( ! RCOfDef->getInterference(LROfDef, LROfUse) ) {
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unsigned CombinedDegree =
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