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a bugfix (up top) and a quick repair job: disable generation of dep.z

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(which died about a week ago) so we're back to load-(2^n-1)-then-AND
sequences. slow, but things should now be Almost Completely Working,
modulo those pesky alignment/ABI issues.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22904 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duraid Madina 2005-08-19 13:25:50 +00:00
parent bfd4f55202
commit a91103430b
1 changed files with 3 additions and 3 deletions
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6
lib/Target/IA64/IA64ISelPattern.cpp
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@ -1220,7 +1220,7 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
case MVT::i16: depositPos=0; depositLen=16; break; case MVT::i16: depositPos=0; depositLen=16; break;
case MVT::i32: depositPos=0; depositLen=32; break; case MVT::i32: depositPos=0; depositLen=32; break;
} }
BuildMI(BB, IA64::DEPZ, 1, Result).addReg(Tmp1) BuildMI(BB, IA64::DEPZ, 3, Result).addReg(Tmp1)
.addImm(depositPos).addImm(depositLen); .addImm(depositPos).addImm(depositLen);
return Result; return Result;
} }
@ -1439,7 +1439,7 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
case MVT::i32: case MVT::i32:
case MVT::i64: { case MVT::i64: {
Tmp1 = SelectExpr(N.getOperand(0)); Tmp1 = SelectExpr(N.getOperand(0));
switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) { /* FIXME switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) {
case 1: // ANDing a constant that is 2^n-1 for some n case 1: // ANDing a constant that is 2^n-1 for some n
switch (Tmp3) { switch (Tmp3) {
case 8: // if AND 0x00000000000000FF, be quaint and use zxt1 case 8: // if AND 0x00000000000000FF, be quaint and use zxt1
@ -1457,7 +1457,7 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
break; break;
} }
return Result; // early exit return Result; // early exit
} // fallthrough and emit a simple AND: FIXME } */ // fallthrough and emit a simple AND:
Tmp2 = SelectExpr(N.getOperand(1)); Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, IA64::AND, 2, Result).addReg(Tmp1).addReg(Tmp2); BuildMI(BB, IA64::AND, 2, Result).addReg(Tmp1).addReg(Tmp2);
} }