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Adjust to change in ctor

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23585 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-10-02 06:23:51 +00:00
parent 4b2e5a680f
commit a916dd8888
1 changed files with 5 additions and 5 deletions
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10
lib/Target/SparcV9/SparcV9RegisterInfo.cpp
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@ -43,7 +43,7 @@ namespace {
SparcV9::g7, SparcV9::o6 SparcV9::g7, SparcV9::o6
}; };
struct IRClass : public TargetRegisterClass { struct IRClass : public TargetRegisterClass {
IRClass() : TargetRegisterClass(8, 8, IR, IR + 32) {} IRClass() : TargetRegisterClass(MVT::i64, 8, 8, IR, IR + 32) {}
} IRInstance; } IRInstance;
@ -71,7 +71,7 @@ namespace {
// one (32, 34, ...), and they must contain double-fp or quad-fp // one (32, 34, ...), and they must contain double-fp or quad-fp
// values... see below about the aliasing problems. // values... see below about the aliasing problems.
struct FRClass : public TargetRegisterClass { struct FRClass : public TargetRegisterClass {
FRClass() : TargetRegisterClass(4, 8, FR, FR + 64) {} FRClass() : TargetRegisterClass(MVT::f32, 4, 8, FR, FR + 64) {}
} FRInstance; } FRInstance;
@ -80,7 +80,7 @@ namespace {
SparcV9::xcc, SparcV9::icc, SparcV9::ccr SparcV9::xcc, SparcV9::icc, SparcV9::ccr
}; };
struct ICCRClass : public TargetRegisterClass { struct ICCRClass : public TargetRegisterClass {
ICCRClass() : TargetRegisterClass(1, 8, ICCR, ICCR + 3) {} ICCRClass() : TargetRegisterClass(MVT::i1, 1, 8, ICCR, ICCR + 3) {}
} ICCRInstance; } ICCRInstance;
@ -89,7 +89,7 @@ namespace {
SparcV9::fcc0, SparcV9::fcc1, SparcV9::fcc2, SparcV9::fcc3 SparcV9::fcc0, SparcV9::fcc1, SparcV9::fcc2, SparcV9::fcc3
}; };
struct FCCRClass : public TargetRegisterClass { struct FCCRClass : public TargetRegisterClass {
FCCRClass() : TargetRegisterClass(1, 8, FCCR, FCCR + 4) {} FCCRClass() : TargetRegisterClass(MVT::i1, 1, 8, FCCR, FCCR + 4) {}
} FCCRInstance; } FCCRInstance;
@ -98,7 +98,7 @@ namespace {
SparcV9::fsr SparcV9::fsr
}; };
struct SRClass : public TargetRegisterClass { struct SRClass : public TargetRegisterClass {
SRClass() : TargetRegisterClass(8, 8, SR, SR + 1) {} SRClass() : TargetRegisterClass(MVT::i64, 8, 8, SR, SR + 1) {}
} SRInstance; } SRInstance;