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https://github.com/c64scene-ar/llvm-6502.git
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Add edges between call instructions and (a) load/store instructions, and
(b) any instructions that use or set CC registers. Whether or not the latter are needed really should be machine-dependent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1008 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve
parent
a2a7094662
commit
a93bbac606
@ -45,7 +45,7 @@ struct RegToRefVecMap: public hash_map<int, RefVec> {
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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SchedGraphEdgeDepType _depType,
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DataDepOrderType _depOrderType,
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unsigned int _depOrderType,
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int _minDelay)
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: src(_src),
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sink(_sink),
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@ -63,7 +63,7 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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const Value* _val,
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DataDepOrderType _depOrderType,
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unsigned int _depOrderType,
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int _minDelay)
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: src(_src),
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sink(_sink),
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@ -81,7 +81,7 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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unsigned int _regNum,
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DataDepOrderType _depOrderType,
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unsigned int _depOrderType,
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int _minDelay)
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: src(_src),
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sink(_sink),
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@ -347,6 +347,7 @@ SchedGraph::addCDEdges(const TerminatorInst* term,
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// Add CD edges from each instruction in the sequence to the
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// *last preceding* branch instr. in the sequence
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// Use a latency of 0 because we only need to prevent out-of-order issue.
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//
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for (int i = (int) termMvec.size()-1; i > (int) first; i--)
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{
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@ -365,7 +366,7 @@ SchedGraph::addCDEdges(const TerminatorInst* term,
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}
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// Add CD edges from each instruction preceding the first branch
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// to the first branch
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// to the first branch. Use a latency of 0 as above.
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//
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for (int i = first-1; i >= 0; i--)
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{
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@ -375,8 +376,8 @@ SchedGraph::addCDEdges(const TerminatorInst* term,
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SchedGraphEdge::NonDataDep, 0);
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}
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// Now add CD edges to the first branch instruction in the sequence
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// from all preceding instructions in the basic block.
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// Now add CD edges to the first branch instruction in the sequence from
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// all preceding instructions in the basic block. Use 0 latency again.
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//
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const BasicBlock* bb = term->getParent();
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for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
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@ -416,6 +417,23 @@ SchedGraph::addCDEdges(const TerminatorInst* term,
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}
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}
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static const int SG_LOAD_REF = 0;
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static const int SG_STORE_REF = 1;
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static const int SG_CALL_REF = 2;
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static const unsigned int SG_DepOrderArray[][3] = {
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{ SchedGraphEdge::NonDataDep,
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SchedGraphEdge::AntiDep,
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SchedGraphEdge::AntiDep },
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{ SchedGraphEdge::TrueDep,
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SchedGraphEdge::OutputDep,
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SchedGraphEdge::TrueDep | SchedGraphEdge::OutputDep },
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{ SchedGraphEdge::TrueDep,
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SchedGraphEdge::AntiDep | SchedGraphEdge::OutputDep,
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SchedGraphEdge::TrueDep | SchedGraphEdge::AntiDep
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| SchedGraphEdge::OutputDep }
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};
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void
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SchedGraph::addMemEdges(const vector<const Instruction*>& memVec,
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@ -426,35 +444,37 @@ SchedGraph::addMemEdges(const vector<const Instruction*>& memVec,
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for (unsigned im=0, NM=memVec.size(); im < NM; im++)
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{
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const Instruction* fromInstr = memVec[im];
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bool fromIsLoad = fromInstr->getOpcode() == Instruction::Load;
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int fromType = (fromInstr->getOpcode() == Instruction::Call
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? SG_CALL_REF
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: (fromInstr->getOpcode() == Instruction::Load
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? SG_LOAD_REF
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: SG_STORE_REF));
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for (unsigned jm=im+1; jm < NM; jm++)
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{
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const Instruction* toInstr = memVec[jm];
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bool toIsLoad = toInstr->getOpcode() == Instruction::Load;
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SchedGraphEdge::DataDepOrderType depOrderType;
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if (fromIsLoad)
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{
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if (toIsLoad) continue; // both instructions are loads
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depOrderType = SchedGraphEdge::AntiDep;
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}
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else
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{
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depOrderType = (toIsLoad)? SchedGraphEdge::TrueDep
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: SchedGraphEdge::OutputDep;
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}
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int toType = (fromInstr->getOpcode() == Instruction::Call? 2
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: ((fromInstr->getOpcode()==Instruction::Load)? 0:1));
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if (fromType == SG_LOAD_REF && toType == SG_LOAD_REF)
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continue;
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unsigned int depOrderType = SG_DepOrderArray[fromType][toType];
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MachineCodeForVMInstr& fromInstrMvec=fromInstr->getMachineInstrVec();
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MachineCodeForVMInstr& toInstrMvec = toInstr->getMachineInstrVec();
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// We have two VM memory instructions, and at least one is a store.
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// Add edges between all machine load/store instructions.
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//
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// We have two VM memory instructions, and at least one is a store
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// or a call. Add edges between all machine load/store/call instrs.
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// Use a latency of 1 to ensure that memory operations are ordered;
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// latency does not otherwise matter (true dependences enforce that).
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//
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for (unsigned i=0, N=fromInstrMvec.size(); i < N; i++)
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{
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MachineOpCode fromOpCode = fromInstrMvec[i]->getOpCode();
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if (mii.isLoad(fromOpCode) || mii.isStore(fromOpCode))
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if (mii.isLoad(fromOpCode) || mii.isStore(fromOpCode) ||
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mii.isCall(fromOpCode))
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{
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SchedGraphNode* fromNode =
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this->getGraphNodeForInstr(fromInstrMvec[i]);
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@ -463,7 +483,8 @@ SchedGraph::addMemEdges(const vector<const Instruction*>& memVec,
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for (unsigned j=0, M=toInstrMvec.size(); j < M; j++)
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{
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MachineOpCode toOpCode = toInstrMvec[j]->getOpCode();
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if (mii.isLoad(toOpCode) || mii.isStore(toOpCode))
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if (mii.isLoad(toOpCode) || mii.isStore(toOpCode)
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|| mii.isCall(fromOpCode))
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{
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SchedGraphNode* toNode =
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this->getGraphNodeForInstr(toInstrMvec[j]);
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@ -481,6 +502,56 @@ SchedGraph::addMemEdges(const vector<const Instruction*>& memVec,
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}
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void
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SchedGraph::addCallCCEdges(const vector<const Instruction*>& memVec,
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MachineCodeForBasicBlock& bbMvec,
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const TargetMachine& target)
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{
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const MachineInstrInfo& mii = target.getInstrInfo();
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vector<SchedGraphNode*> callNodeVec;
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// Find the call machine instructions and put them in a vector.
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// By using memVec, we avoid searching the entire machine code of the BB.
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//
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for (unsigned im=0, NM=memVec.size(); im < NM; im++)
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if (memVec[im]->getOpcode() == Instruction::Call)
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{
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MachineCodeForVMInstr& callMvec=memVec[im]->getMachineInstrVec();
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for (unsigned i=0; i < callMvec.size(); ++i)
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if (mii.isCall(callMvec[i]->getOpCode()))
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callNodeVec.push_back(this->getGraphNodeForInstr(callMvec[i]));
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}
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// Now add additional edges from/to CC reg instrs to/from call instrs.
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// Essentially this prevents anything that sets or uses a CC reg from being
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// reordered w.r.t. a call.
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// Use a latency of 0 because we only need to prevent out-of-order issue,
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// like with control dependences.
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//
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int lastCallNodeIdx = -1;
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for (unsigned i=0, N=bbMvec.size(); i < N; i++)
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if (mii.isCall(bbMvec[i]->getOpCode()))
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{
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++lastCallNodeIdx;
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for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
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if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
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break;
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assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
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}
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else if (mii.isCCInstr(bbMvec[i]->getOpCode()))
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{ // Add incoming/outgoing edges from/to preceding/later calls
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SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
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int j=0;
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for ( ; j <= lastCallNodeIdx; j++)
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(void) new SchedGraphEdge(callNodeVec[j], ccNode,
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MachineCCRegsRID, 0);
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for ( ; j < (int) callNodeVec.size(); j++)
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(void) new SchedGraphEdge(ccNode, callNodeVec[j],
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MachineCCRegsRID, 0);
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}
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}
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void
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SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
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const TargetMachine& target)
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@ -749,7 +820,7 @@ SchedGraph::buildGraph(const TargetMachine& target)
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assert(bbVec.size() == 1 && "Only handling a single basic block here");
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// Use this data structures to note all LLVM memory instructions.
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// Use these data structures to note all LLVM memory instructions.
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// We use this to add memory dependence edges without a second full walk.
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//
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vector<const Instruction*> memVec;
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@ -782,11 +853,12 @@ SchedGraph::buildGraph(const TargetMachine& target)
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// Build graph nodes for this VM instruction
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buildNodesforVMInstr(target, instr);
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// Remember the load/store instructions to add memory deps later.
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// Remember the load/store/call instructions to add memory deps later.
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if (instr->getOpcode() == Instruction::Load ||
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instr->getOpcode() == Instruction::Store)
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instr->getOpcode() == Instruction::Store ||
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instr->getOpcode() == Instruction::Call)
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memVec.push_back(instr);
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}
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}
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//----------------------------------------------------------------
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// Now add edges for the following (all are incoming edges except (4)):
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@ -804,17 +876,22 @@ SchedGraph::buildGraph(const TargetMachine& target)
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//
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//----------------------------------------------------------------
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MachineCodeForBasicBlock& bbMvec = bb->getMachineInstrVec();
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// First, add edges to the terminator instruction of the basic block.
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this->addCDEdges(bb->getTerminator(), target);
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// Then add memory dep edges: store->load, load->store, and store->store
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// Then add memory dep edges: store->load, load->store, and store->store.
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// Call instructions are treated as both load and store.
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this->addMemEdges(memVec, target);
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// Then add edges between call instructions and CC set/use instructions
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this->addCallCCEdges(memVec, bbMvec, target);
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// Then add other edges for all instructions in the block.
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// Do this in machine code order and find all references to machine regs.
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MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
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for (unsigned i=0, N=mvec.size(); i < N; i++)
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addEdgesForInstruction(*mvec[i], regToRefVecMap, target);
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for (unsigned i=0, N=bbMvec.size(); i < N; i++)
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addEdgesForInstruction(*bbMvec[i], regToRefVecMap, target);
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// Since the code is no longer in SSA form, add output dep. edges
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// between machine instructions that define the same Value, and anti-dep.
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@ -45,7 +45,7 @@ struct RegToRefVecMap: public hash_map<int, RefVec> {
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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SchedGraphEdgeDepType _depType,
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DataDepOrderType _depOrderType,
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unsigned int _depOrderType,
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int _minDelay)
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: src(_src),
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sink(_sink),
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@ -63,7 +63,7 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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const Value* _val,
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DataDepOrderType _depOrderType,
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unsigned int _depOrderType,
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int _minDelay)
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: src(_src),
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sink(_sink),
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@ -81,7 +81,7 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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unsigned int _regNum,
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DataDepOrderType _depOrderType,
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unsigned int _depOrderType,
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int _minDelay)
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: src(_src),
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sink(_sink),
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@ -347,6 +347,7 @@ SchedGraph::addCDEdges(const TerminatorInst* term,
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// Add CD edges from each instruction in the sequence to the
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// *last preceding* branch instr. in the sequence
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// Use a latency of 0 because we only need to prevent out-of-order issue.
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//
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for (int i = (int) termMvec.size()-1; i > (int) first; i--)
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{
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@ -365,7 +366,7 @@ SchedGraph::addCDEdges(const TerminatorInst* term,
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}
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// Add CD edges from each instruction preceding the first branch
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// to the first branch
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// to the first branch. Use a latency of 0 as above.
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//
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for (int i = first-1; i >= 0; i--)
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{
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@ -375,8 +376,8 @@ SchedGraph::addCDEdges(const TerminatorInst* term,
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SchedGraphEdge::NonDataDep, 0);
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}
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// Now add CD edges to the first branch instruction in the sequence
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// from all preceding instructions in the basic block.
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// Now add CD edges to the first branch instruction in the sequence from
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// all preceding instructions in the basic block. Use 0 latency again.
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//
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const BasicBlock* bb = term->getParent();
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for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
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@ -416,6 +417,23 @@ SchedGraph::addCDEdges(const TerminatorInst* term,
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}
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}
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static const int SG_LOAD_REF = 0;
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static const int SG_STORE_REF = 1;
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static const int SG_CALL_REF = 2;
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static const unsigned int SG_DepOrderArray[][3] = {
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{ SchedGraphEdge::NonDataDep,
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SchedGraphEdge::AntiDep,
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SchedGraphEdge::AntiDep },
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{ SchedGraphEdge::TrueDep,
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SchedGraphEdge::OutputDep,
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SchedGraphEdge::TrueDep | SchedGraphEdge::OutputDep },
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{ SchedGraphEdge::TrueDep,
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SchedGraphEdge::AntiDep | SchedGraphEdge::OutputDep,
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SchedGraphEdge::TrueDep | SchedGraphEdge::AntiDep
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| SchedGraphEdge::OutputDep }
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};
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void
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SchedGraph::addMemEdges(const vector<const Instruction*>& memVec,
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@ -426,35 +444,37 @@ SchedGraph::addMemEdges(const vector<const Instruction*>& memVec,
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for (unsigned im=0, NM=memVec.size(); im < NM; im++)
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{
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const Instruction* fromInstr = memVec[im];
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bool fromIsLoad = fromInstr->getOpcode() == Instruction::Load;
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int fromType = (fromInstr->getOpcode() == Instruction::Call
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? SG_CALL_REF
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: (fromInstr->getOpcode() == Instruction::Load
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? SG_LOAD_REF
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: SG_STORE_REF));
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for (unsigned jm=im+1; jm < NM; jm++)
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{
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const Instruction* toInstr = memVec[jm];
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bool toIsLoad = toInstr->getOpcode() == Instruction::Load;
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SchedGraphEdge::DataDepOrderType depOrderType;
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if (fromIsLoad)
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{
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if (toIsLoad) continue; // both instructions are loads
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depOrderType = SchedGraphEdge::AntiDep;
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}
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else
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{
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depOrderType = (toIsLoad)? SchedGraphEdge::TrueDep
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: SchedGraphEdge::OutputDep;
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}
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int toType = (fromInstr->getOpcode() == Instruction::Call? 2
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: ((fromInstr->getOpcode()==Instruction::Load)? 0:1));
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if (fromType == SG_LOAD_REF && toType == SG_LOAD_REF)
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continue;
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unsigned int depOrderType = SG_DepOrderArray[fromType][toType];
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MachineCodeForVMInstr& fromInstrMvec=fromInstr->getMachineInstrVec();
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MachineCodeForVMInstr& toInstrMvec = toInstr->getMachineInstrVec();
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// We have two VM memory instructions, and at least one is a store.
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// Add edges between all machine load/store instructions.
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//
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// We have two VM memory instructions, and at least one is a store
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// or a call. Add edges between all machine load/store/call instrs.
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// Use a latency of 1 to ensure that memory operations are ordered;
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// latency does not otherwise matter (true dependences enforce that).
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//
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for (unsigned i=0, N=fromInstrMvec.size(); i < N; i++)
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{
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MachineOpCode fromOpCode = fromInstrMvec[i]->getOpCode();
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if (mii.isLoad(fromOpCode) || mii.isStore(fromOpCode))
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if (mii.isLoad(fromOpCode) || mii.isStore(fromOpCode) ||
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mii.isCall(fromOpCode))
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{
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SchedGraphNode* fromNode =
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this->getGraphNodeForInstr(fromInstrMvec[i]);
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@ -463,7 +483,8 @@ SchedGraph::addMemEdges(const vector<const Instruction*>& memVec,
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for (unsigned j=0, M=toInstrMvec.size(); j < M; j++)
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{
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MachineOpCode toOpCode = toInstrMvec[j]->getOpCode();
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if (mii.isLoad(toOpCode) || mii.isStore(toOpCode))
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if (mii.isLoad(toOpCode) || mii.isStore(toOpCode)
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|| mii.isCall(fromOpCode))
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{
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SchedGraphNode* toNode =
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this->getGraphNodeForInstr(toInstrMvec[j]);
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@ -481,6 +502,56 @@ SchedGraph::addMemEdges(const vector<const Instruction*>& memVec,
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}
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void
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SchedGraph::addCallCCEdges(const vector<const Instruction*>& memVec,
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MachineCodeForBasicBlock& bbMvec,
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const TargetMachine& target)
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{
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const MachineInstrInfo& mii = target.getInstrInfo();
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vector<SchedGraphNode*> callNodeVec;
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// Find the call machine instructions and put them in a vector.
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// By using memVec, we avoid searching the entire machine code of the BB.
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//
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for (unsigned im=0, NM=memVec.size(); im < NM; im++)
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if (memVec[im]->getOpcode() == Instruction::Call)
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{
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MachineCodeForVMInstr& callMvec=memVec[im]->getMachineInstrVec();
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for (unsigned i=0; i < callMvec.size(); ++i)
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if (mii.isCall(callMvec[i]->getOpCode()))
|
||||
callNodeVec.push_back(this->getGraphNodeForInstr(callMvec[i]));
|
||||
}
|
||||
|
||||
// Now add additional edges from/to CC reg instrs to/from call instrs.
|
||||
// Essentially this prevents anything that sets or uses a CC reg from being
|
||||
// reordered w.r.t. a call.
|
||||
// Use a latency of 0 because we only need to prevent out-of-order issue,
|
||||
// like with control dependences.
|
||||
//
|
||||
int lastCallNodeIdx = -1;
|
||||
for (unsigned i=0, N=bbMvec.size(); i < N; i++)
|
||||
if (mii.isCall(bbMvec[i]->getOpCode()))
|
||||
{
|
||||
++lastCallNodeIdx;
|
||||
for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
|
||||
if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
|
||||
break;
|
||||
assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
|
||||
}
|
||||
else if (mii.isCCInstr(bbMvec[i]->getOpCode()))
|
||||
{ // Add incoming/outgoing edges from/to preceding/later calls
|
||||
SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
|
||||
int j=0;
|
||||
for ( ; j <= lastCallNodeIdx; j++)
|
||||
(void) new SchedGraphEdge(callNodeVec[j], ccNode,
|
||||
MachineCCRegsRID, 0);
|
||||
for ( ; j < (int) callNodeVec.size(); j++)
|
||||
(void) new SchedGraphEdge(ccNode, callNodeVec[j],
|
||||
MachineCCRegsRID, 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
|
||||
const TargetMachine& target)
|
||||
@ -749,7 +820,7 @@ SchedGraph::buildGraph(const TargetMachine& target)
|
||||
|
||||
assert(bbVec.size() == 1 && "Only handling a single basic block here");
|
||||
|
||||
// Use this data structures to note all LLVM memory instructions.
|
||||
// Use these data structures to note all LLVM memory instructions.
|
||||
// We use this to add memory dependence edges without a second full walk.
|
||||
//
|
||||
vector<const Instruction*> memVec;
|
||||
@ -782,11 +853,12 @@ SchedGraph::buildGraph(const TargetMachine& target)
|
||||
// Build graph nodes for this VM instruction
|
||||
buildNodesforVMInstr(target, instr);
|
||||
|
||||
// Remember the load/store instructions to add memory deps later.
|
||||
// Remember the load/store/call instructions to add memory deps later.
|
||||
if (instr->getOpcode() == Instruction::Load ||
|
||||
instr->getOpcode() == Instruction::Store)
|
||||
instr->getOpcode() == Instruction::Store ||
|
||||
instr->getOpcode() == Instruction::Call)
|
||||
memVec.push_back(instr);
|
||||
}
|
||||
}
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// Now add edges for the following (all are incoming edges except (4)):
|
||||
@ -804,17 +876,22 @@ SchedGraph::buildGraph(const TargetMachine& target)
|
||||
//
|
||||
//----------------------------------------------------------------
|
||||
|
||||
MachineCodeForBasicBlock& bbMvec = bb->getMachineInstrVec();
|
||||
|
||||
// First, add edges to the terminator instruction of the basic block.
|
||||
this->addCDEdges(bb->getTerminator(), target);
|
||||
|
||||
// Then add memory dep edges: store->load, load->store, and store->store
|
||||
// Then add memory dep edges: store->load, load->store, and store->store.
|
||||
// Call instructions are treated as both load and store.
|
||||
this->addMemEdges(memVec, target);
|
||||
|
||||
|
||||
// Then add edges between call instructions and CC set/use instructions
|
||||
this->addCallCCEdges(memVec, bbMvec, target);
|
||||
|
||||
// Then add other edges for all instructions in the block.
|
||||
// Do this in machine code order and find all references to machine regs.
|
||||
MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
|
||||
for (unsigned i=0, N=mvec.size(); i < N; i++)
|
||||
addEdgesForInstruction(*mvec[i], regToRefVecMap, target);
|
||||
for (unsigned i=0, N=bbMvec.size(); i < N; i++)
|
||||
addEdgesForInstruction(*bbMvec[i], regToRefVecMap, target);
|
||||
|
||||
// Since the code is no longer in SSA form, add output dep. edges
|
||||
// between machine instructions that define the same Value, and anti-dep.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user