6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-26 07:24:25 +00:00
Code Issues Projects Releases Wiki Activity

Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.

Browse Source 
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.

rdar://problem/9240648


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2011-04-06 18:27:46 +00:00
parent 3d195faaad
commit a9611549fe
3 changed files with 6 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -3037,7 +3037,7 @@ static bool DisassembleNGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
ElemSize esize =
Opcode == ARM::VGETLNi32 ? ESize32
: ((Opcode == ARM::VGETLNs16 || Opcode == ARM::VGETLNu16) ? ESize16
: ESize32);
: ESize8);
// Rt = Inst{15-12} => ARM Rd
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,