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Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.

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Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.

rdar://problem/9240648


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-06 18:27:46 +00:00
parent 3d195faaad
commit a9611549fe
3 changed files with 6 additions and 1 deletions
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2
lib/Target/ARM/ARMInstrFormats.td
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@ -1850,6 +1850,8 @@ class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
let Inst{11-8} = opcod2; let Inst{11-8} = opcod2;
let Inst{6-5} = opcod3; let Inst{6-5} = opcod3;
let Inst{4} = 1; let Inst{4} = 1;
// A8.6.303, A8.6.328, A8.6.329
let Inst{3-0} = 0b0000;
let OutOperandList = oops; let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p)); let InOperandList = !con(iops, (ins pred:$p));

2
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -3037,7 +3037,7 @@ static bool DisassembleNGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
ElemSize esize = ElemSize esize =
Opcode == ARM::VGETLNi32 ? ESize32 Opcode == ARM::VGETLNi32 ? ESize32
: ((Opcode == ARM::VGETLNs16 || Opcode == ARM::VGETLNu16) ? ESize16 : ((Opcode == ARM::VGETLNs16 || Opcode == ARM::VGETLNu16) ? ESize16
: ESize32); : ESize8);
// Rt = Inst{15-12} => ARM Rd // Rt = Inst{15-12} => ARM Rd
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,

3
test/MC/Disassembler/ARM/neon-tests.txt
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@ -71,3 +71,6 @@
# CHECK: vst2.32 {d16, d18}, [r2, :64], r2 # CHECK: vst2.32 {d16, d18}, [r2, :64], r2
0x92 0x9 0x42 0xf4 0x92 0x9 0x42 0xf4
# CHECK: vmov.s8 r0, d8[1]
0x30 0x0b 0x58 0xee