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(or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121606 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-12-11 04:11:38 +00:00
parent 533f58ecdd
commit a9688c4b57
4 changed files with 62 additions and 19 deletions
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35
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -4727,16 +4727,37 @@ static SDValue PerformORCombine(SDNode *N,
// Case (1): or (and A, mask), val => ARMbfi A, val, mask
if ((C = dyn_cast<ConstantSDNode>(N1))) {
unsigned Val = C->getZExtValue();
if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val)
if ((Val & ~Mask) != Val)
return SDValue();
Val >>= CountTrailingZeros_32(~Mask);
Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
DAG.getConstant(Val, MVT::i32),
DAG.getConstant(Mask, MVT::i32));
if (ARM::isBitFieldInvertedMask(Mask)) {
Val >>= CountTrailingZeros_32(~Mask);
// Do not add new nodes to DAG combiner worklist.
DCI.CombineTo(N, Res, false);
Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
DAG.getConstant(Val, MVT::i32),
DAG.getConstant(Mask, MVT::i32));
// Do not add new nodes to DAG combiner worklist.
DCI.CombineTo(N, Res, false);
} else if (N0.getOperand(0).getOpcode() == ISD::SHL &&
isa<ConstantSDNode>(N0.getOperand(0).getOperand(1)) &&
ARM::isBitFieldInvertedMask(~Mask)) {
// Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
// where lsb(mask) == #shamt
SDValue ShAmt = N0.getOperand(0).getOperand(1);
unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
unsigned LSB = CountTrailingZeros_32(Mask);
if (ShAmtC != LSB)
return SDValue();
//unsigned Width = (32 - CountLeadingZeros_32(Mask)) - LSB;
Res = DAG.getNode(ARMISD::BFI, DL, VT, N1,
N0.getOperand(0).getOperand(0),
DAG.getConstant(~Mask, MVT::i32));
// Do not add new nodes to DAG combiner worklist.
DCI.CombineTo(N, Res, false);
}
} else if (N1.getOpcode() == ISD::AND) {
// case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
C = dyn_cast<ConstantSDNode>(N1.getOperand(1));

20
lib/Target/ARM/ARMInstrInfo.td
View File

@ -225,16 +225,6 @@ def sext_16_node : PatLeaf<(i32 GPR:$a), [{
return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
}]>;
/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
/// e.g., 0xf000ffff
def bf_inv_mask_imm : Operand<i32>,
PatLeaf<(imm), [{
return ARM::isBitFieldInvertedMask(N->getZExtValue());
}] > {
let EncoderMethod = "getBitfieldInvertedMaskOpValue";
let PrintMethod = "printBitfieldInvMaskImmOperand";
}
/// Split a 32-bit immediate into two 16 bit parts.
def hi16 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
@ -462,6 +452,16 @@ def movt_imm : Operand<i32> {
let EncoderMethod = "getMovtImmOpValue";
}
/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
/// e.g., 0xf000ffff
def bf_inv_mask_imm : Operand<i32>,
PatLeaf<(imm), [{
return ARM::isBitFieldInvertedMask(N->getZExtValue());
}] > {
let EncoderMethod = "getBitfieldInvertedMaskOpValue";
let PrintMethod = "printBitfieldInvMaskImmOperand";
}
// Define ARM specific addressing modes.

15
test/CodeGen/ARM/bfi.ll
View File

@ -16,7 +16,7 @@ entry:
ret void
}
define i32 @f2(i32 %A, i32 %B) nounwind readnone optsize {
define i32 @f2(i32 %A, i32 %B) nounwind {
entry:
; CHECK: f2
; CHECK: lsr{{.*}}#7
@ -27,7 +27,7 @@ entry:
ret i32 %or
}
define i32 @f3(i32 %A, i32 %B) nounwind readnone optsize {
define i32 @f3(i32 %A, i32 %B) nounwind {
entry:
; CHECK: f3
; CHECK: lsr{{.*}} #7
@ -38,3 +38,14 @@ entry:
%or = or i32 %and2, %and ; <i32> [#uses=1]
ret i32 %or
}
; rdar://8752056
define i32 @f4(i32 %a) nounwind {
; CHECK: f4
; CHECK: movw r1, #3137
; CHECK: bfi r1, r0, #15, #5
%1 = shl i32 %a, 15
%ins7 = and i32 %1, 1015808
%ins12 = or i32 %ins7, 3137
ret i32 %ins12
}

11
test/CodeGen/Thumb2/bfi.ll
View File

@ -38,3 +38,14 @@ entry:
%or = or i32 %and2, %and ; <i32> [#uses=1]
ret i32 %or
}
; rdar://8752056
define i32 @f4(i32 %a) nounwind {
; CHECK: f4
; CHECK: movw r1, #3137
; CHECK: bfi r1, r0, #15, #5
%1 = shl i32 %a, 15
%ins7 = and i32 %1, 1015808
%ins12 = or i32 %ins7, 3137
ret i32 %ins12
}