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Back out branchless SetCC code. While it helped a lot in some cases, it
hurt a lot in others. Instead, improve branching version of SetCC and Select instructions. The old code will be in CVS should we ever need to dig it up again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15979 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
b586c08d53
commit
a96c4af7f1
@ -1110,148 +1110,12 @@ void ISel::visitSetCondInst(SetCondInst &I) {
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if (canFoldSetCCIntoBranchOrSelect(&I))
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return;
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Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
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const Type *Ty = Op0->getType();
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unsigned Class = getClassB(Ty);
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unsigned Opcode = I.getOpcode();
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unsigned DestReg = getReg(I);
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// If the comparison type is byte, short, or int, then we can emit a
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// branchless version of the SetCC that puts 0 (false) or 1 (true) in the
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// destination register.
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if (Class <= cInt) {
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++NumSetCC;
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MachineBasicBlock::iterator MI = BB->end();
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unsigned OpNum = getSetCCNumber(Opcode);
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unsigned Op0Reg = getReg(Op0, BB, MI);
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Op0Reg = ExtendOrClear(BB, MI, Op0Reg, Ty);
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// comparisons against constant zero often have shorter sequences than the
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// general case, handled below.
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ConstantInt *CI = dyn_cast<ConstantInt>(Op1);
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if (CI && CI->getRawValue() == 0) {
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switch(OpNum) {
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case 0: { // eq0
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unsigned TempReg = makeAnotherReg(Type::IntTy);
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BuildMI(*BB, MI, PPC::CNTLZW, 1, TempReg).addReg(Op0Reg);
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BuildMI(*BB, MI, PPC::SRWI, 2, DestReg).addReg(TempReg).addImm(5);
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break;
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}
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case 1: { // ne0
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unsigned TempReg = makeAnotherReg(Type::IntTy);
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BuildMI(*BB, MI, PPC::ADDIC, 2, TempReg).addReg(Op0Reg).addSImm(-1);
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BuildMI(*BB, MI, PPC::SUBFE, 2, DestReg).addReg(TempReg).addReg(Op0Reg);
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break;
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}
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case 2: { // lt0, always false if unsigned
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if (Ty->isSigned())
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BuildMI(*BB, MI, PPC::SRWI, 2, DestReg).addReg(Op0Reg).addImm(31);
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else
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BuildMI(*BB, MI, PPC::LI, 1, DestReg).addSImm(0);
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break;
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}
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case 3: { // ge0, always true if unsigned
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if (Ty->isSigned()) {
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unsigned TempReg = makeAnotherReg(Type::IntTy);
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BuildMI(*BB, MI, PPC::SRWI, 2, TempReg).addReg(Op0Reg).addImm(31);
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BuildMI(*BB, MI, PPC::XORI, 2, DestReg).addReg(TempReg).addImm(1);
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} else {
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BuildMI(*BB, MI, PPC::LI, 1, DestReg).addSImm(1);
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}
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break;
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}
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case 4: { // gt0, equivalent to ne0 if unsigned
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unsigned Temp1 = makeAnotherReg(Type::IntTy);
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unsigned Temp2 = makeAnotherReg(Type::IntTy);
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if (Ty->isSigned()) {
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BuildMI(*BB, MI, PPC::NEG, 2, Temp1).addReg(Op0Reg);
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BuildMI(*BB, MI, PPC::ANDC, 2, Temp2).addReg(Temp1).addReg(Op0Reg);
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BuildMI(*BB, MI, PPC::SRWI, 2, DestReg).addReg(Temp2).addImm(31);
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} else {
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BuildMI(*BB, MI, PPC::ADDIC, 2, Temp1).addReg(Op0Reg).addSImm(-1);
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BuildMI(*BB, MI, PPC::SUBFE, 2, DestReg).addReg(Temp1).addReg(Op0Reg);
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}
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break;
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}
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case 5: { // le0, equivalent to eq0 if unsigned
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unsigned Temp1 = makeAnotherReg(Type::IntTy);
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unsigned Temp2 = makeAnotherReg(Type::IntTy);
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if (Ty->isSigned()) {
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BuildMI(*BB, MI, PPC::NEG, 2, Temp1).addReg(Op0Reg);
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BuildMI(*BB, MI, PPC::ORC, 2, Temp2).addReg(Op0Reg).addReg(Temp1);
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BuildMI(*BB, MI, PPC::SRWI, 2, DestReg).addReg(Temp2).addImm(31);
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} else {
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BuildMI(*BB, MI, PPC::CNTLZW, 1, Temp1).addReg(Op0Reg);
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BuildMI(*BB, MI, PPC::SRWI, 2, DestReg).addReg(Temp1).addImm(5);
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}
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break;
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}
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} // switch
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return;
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}
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unsigned Op1Reg = getReg(Op1, BB, MI);
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switch(OpNum) {
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case 0: { // eq
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unsigned Temp1 = makeAnotherReg(Type::IntTy);
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unsigned Temp2 = makeAnotherReg(Type::IntTy);
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BuildMI(*BB, MI, PPC::SUBF, 2, Temp1).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(*BB, MI, PPC::CNTLZW, 1, Temp2).addReg(Temp1);
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BuildMI(*BB, MI, PPC::SRWI, 2, DestReg).addReg(Temp2).addImm(5);
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break;
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}
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case 1: { // ne
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unsigned Temp1 = makeAnotherReg(Type::IntTy);
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unsigned Temp2 = makeAnotherReg(Type::IntTy);
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BuildMI(*BB, MI, PPC::SUBF, 2, Temp1).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(*BB, MI, PPC::ADDIC, 2, Temp2).addReg(Temp1).addSImm(-1);
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BuildMI(*BB, MI, PPC::SUBFE, 2, DestReg).addReg(Temp2).addReg(Temp1);
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break;
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}
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case 2:
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case 4: { // lt, gt
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unsigned Temp1 = makeAnotherReg(Type::IntTy);
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unsigned Temp2 = makeAnotherReg(Type::IntTy);
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unsigned Temp3 = makeAnotherReg(Type::IntTy);
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unsigned Temp4 = makeAnotherReg(Type::IntTy);
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if (OpNum == 4) std::swap(Op0Reg, Op1Reg);
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if (Ty->isSigned()) {
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BuildMI(*BB, MI, PPC::SUBFC, 2, Temp1).addReg(Op1Reg).addReg(Op0Reg);
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BuildMI(*BB, MI, PPC::EQV, 2, Temp2).addReg(Op1Reg).addReg(Op0Reg);
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BuildMI(*BB, MI, PPC::SRWI, 2, Temp3).addReg(Temp2).addImm(31);
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BuildMI(*BB, MI, PPC::ADDZE, 1, Temp4).addReg(Temp3);
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BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Temp4).addImm(0)
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.addImm(31).addImm(31);
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} else {
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BuildMI(*BB, MI, PPC::SUBFC, 2, Temp1).addReg(Op1Reg).addReg(Op0Reg);
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BuildMI(*BB, MI, PPC::SUBFE, 2, Temp2).addReg(Temp1).addReg(Temp1);
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BuildMI(*BB, MI, PPC::NEG, 2, DestReg).addReg(Temp2);
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}
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break;
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}
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case 3:
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case 5: { // le, ge
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unsigned Temp1 = makeAnotherReg(Type::IntTy);
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unsigned Temp2 = makeAnotherReg(Type::IntTy);
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unsigned Temp3 = makeAnotherReg(Type::IntTy);
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if (OpNum == 3) std::swap(Op0Reg, Op1Reg);
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if (Ty->isSigned()) {
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BuildMI(*BB, MI, PPC::SRWI, 2, Temp1).addReg(Op0Reg).addImm(31);
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BuildMI(*BB, MI, PPC::SRAWI, 2, Temp2).addReg(Op1Reg).addImm(31);
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BuildMI(*BB, MI, PPC::SUBFC, 2, Temp3).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(*BB, MI, PPC::ADDE, 2, DestReg).addReg(Temp2).addReg(Temp1);
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} else {
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BuildMI(*BB, MI, PPC::LI, 1, Temp2).addSImm(-1);
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BuildMI(*BB, MI, PPC::SUBFC, 2, Temp1).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(*BB, MI, PPC::SUBFZE, 1, DestReg).addReg(Temp2);
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}
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break;
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}
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} // switch
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return;
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}
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EmitComparison(Opcode, Op0, Op1, BB, BB->end());
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unsigned Opcode = I.getOpcode();
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unsigned PPCOpcode = getPPCOpcodeForSetCCNumber(Opcode);
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// Create an iterator with which to insert the MBB for copying the false value
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// and the MBB to hold the PHI instruction for this SetCC.
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MachineBasicBlock *thisMBB = BB;
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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ilist<MachineBasicBlock>::iterator It = BB;
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@ -1260,32 +1124,18 @@ void ISel::visitSetCondInst(SetCondInst &I) {
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// thisMBB:
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// ...
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// cmpTY cr0, r1, r2
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// bCC copy1MBB
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// b copy0MBB
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// FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
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// if we could insert other, non-terminator instructions after the
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// bCC. But MBB->getFirstTerminator() can't understand this.
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MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
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F->getBasicBlockList().insert(It, copy1MBB);
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BuildMI(BB, PPCOpcode, 2).addReg(PPC::CR0).addMBB(copy1MBB);
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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F->getBasicBlockList().insert(It, copy0MBB);
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BuildMI(BB, PPC::B, 1).addMBB(copy0MBB);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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F->getBasicBlockList().insert(It, sinkMBB);
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// Update machine-CFG edges
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BB->addSuccessor(copy1MBB);
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BB->addSuccessor(copy0MBB);
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// copy1MBB:
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// %TrueValue = li 1
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// b sinkMBB
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BB = copy1MBB;
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// bCC sinkMBB
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EmitComparison(Opcode, I.getOperand(0), I.getOperand(1), BB, BB->end());
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unsigned TrueValue = makeAnotherReg(I.getType());
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BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
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BuildMI(BB, PPC::B, 1).addMBB(sinkMBB);
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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BuildMI(BB, PPCOpcode, 2).addReg(PPC::CR0).addMBB(sinkMBB);
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F->getBasicBlockList().insert(It, copy0MBB);
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F->getBasicBlockList().insert(It, sinkMBB);
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// Update machine-CFG edges
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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// copy0MBB:
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@ -1298,11 +1148,11 @@ void ISel::visitSetCondInst(SetCondInst &I) {
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BB = sinkMBB;
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BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
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.addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
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.addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
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}
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void ISel::visitSelectInst(SelectInst &SI) {
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@ -1335,40 +1185,25 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
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BuildMI(*MBB, IP, PPC::CMPI, 2, PPC::CR0).addReg(CondReg).addSImm(0);
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Opcode = getPPCOpcodeForSetCCNumber(Instruction::SetNE);
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}
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// thisMBB:
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// ...
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// cmpTY cr0, r1, r2
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// bCC copy1MBB
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// b copy0MBB
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unsigned TrueValue = getReg(TrueVal, BB, BB->end());
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MachineBasicBlock *thisMBB = BB;
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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ilist<MachineBasicBlock>::iterator It = BB;
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++It;
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// FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
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// if we could insert other, non-terminator instructions after the
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// bCC. But MBB->getFirstTerminator() can't understand this.
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MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
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F->getBasicBlockList().insert(It, copy1MBB);
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BuildMI(BB, Opcode, 2).addReg(PPC::CR0).addMBB(copy1MBB);
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// thisMBB:
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// ...
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// cmpTY cr0, r1, r2
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// %TrueValue = ...
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// bCC sinkMBB
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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F->getBasicBlockList().insert(It, copy0MBB);
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BuildMI(BB, PPC::B, 1).addMBB(copy0MBB);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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BuildMI(BB, Opcode, 2).addReg(PPC::CR0).addMBB(sinkMBB);
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F->getBasicBlockList().insert(It, copy0MBB);
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F->getBasicBlockList().insert(It, sinkMBB);
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// Update machine-CFG edges
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BB->addSuccessor(copy1MBB);
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BB->addSuccessor(copy0MBB);
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// copy1MBB:
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// %TrueValue = ...
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// b sinkMBB
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BB = copy1MBB;
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unsigned TrueValue = getReg(TrueVal, BB, BB->begin());
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BuildMI(BB, PPC::B, 1).addMBB(sinkMBB);
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// copy0MBB:
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@ -1380,12 +1215,14 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BB = sinkMBB;
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BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
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.addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
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.addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
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// For a register pair representing a long value, define the second reg
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// FIXME: Can this really be correct for selecting longs?
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if (getClassB(TrueVal->getType()) == cLong)
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BuildMI(BB, PPC::LI, 1, DestReg+1).addImm(0);
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return;
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