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https://github.com/c64scene-ar/llvm-6502.git
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Add 128-bit integer vector load and add (for testing).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26967 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -290,14 +290,20 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::ADD, MVT::v2f64, Legal);
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setOperationAction(ISD::ADD, MVT::v16i8, Legal);
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setOperationAction(ISD::ADD, MVT::v8i16, Legal);
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setOperationAction(ISD::ADD, MVT::v4i32, Legal);
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setOperationAction(ISD::SUB, MVT::v2f64, Legal);
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setOperationAction(ISD::MUL, MVT::v2f64, Legal);
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setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
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setOperationAction(ISD::LOAD, MVT::v16i8, Legal);
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setOperationAction(ISD::LOAD, MVT::v8i16, Legal);
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setOperationAction(ISD::LOAD, MVT::v4i32, Legal);
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setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Expand);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
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@ -770,6 +770,32 @@ def MOVQ128rm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
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def MOVQ128mr : PDI<0xD6, MRMSrcMem, (ops i64mem:$dst, VR128:$src),
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"movq {$src, $dst|$dst, $src}", []>;
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// 128-bit Integer Arithmetic
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let isTwoAddress = 1 in {
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let isCommutable = 1 in {
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def PADDBrr : PDI<0xFC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"paddb {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v16i8 (add VR128:$src1, VR128:$src2)))]>;
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def PADDWrr : PDI<0xFD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"paddw {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v8i16 (add VR128:$src1, VR128:$src2)))]>;
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def PADDDrr : PDI<0xFE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"paddd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v4i32 (add VR128:$src1, VR128:$src2)))]>;
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}
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def PADDBrm : PDI<0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"paddb {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v16i8 (add VR128:$src1,
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(load addr:$src2))))]>;
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def PADDWrm : PDI<0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"paddw {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v8i16 (add VR128:$src1,
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(load addr:$src2))))]>;
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def PADDDrm : PDI<0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"paddd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v4i32 (add VR128:$src1,
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(load addr:$src2))))]>;
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}
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//===----------------------------------------------------------------------===//
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// Alias Instructions
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@ -796,11 +822,25 @@ def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
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def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
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def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
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// Load 128-bit integer vector values.
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def : Pat<(v16i8 (load addr:$src)), (MOVAPSrm addr:$src)>,
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Requires<[HasSSE1]>;
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def : Pat<(v8i16 (load addr:$src)), (MOVAPSrm addr:$src)>,
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Requires<[HasSSE1]>;
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def : Pat<(v4i32 (load addr:$src)), (MOVAPSrm addr:$src)>,
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Requires<[HasSSE1]>;
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def : Pat<(v2i64 (load addr:$src)), (MOVAPDrm addr:$src)>,
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Requires<[HasSSE2]>;
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// Store 128-bit integer vector values.
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def : Pat<(store (v16i8 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst, VR128:$src)>;
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def : Pat<(store (v8i16 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst, VR128:$src)>;
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def : Pat<(store (v4i32 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst, VR128:$src)>;
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def : Pat<(store (v2i64 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst, VR128:$src)>;
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def : Pat<(store (v16i8 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst, VR128:$src)>,
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Requires<[HasSSE1]>;
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def : Pat<(store (v8i16 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst, VR128:$src)>,
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Requires<[HasSSE1]>;
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def : Pat<(store (v4i32 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst, VR128:$src)>,
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Requires<[HasSSE1]>;
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def : Pat<(store (v2i64 VR128:$src), addr:$dst), (MOVAPDmr addr:$dst, VR128:$src)>,
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Requires<[HasSSE2]>;
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// Scalar to v8i16 / v16i8. The source may be a R32, but only the lower 8 or
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// 16-bits matter.
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