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https://github.com/c64scene-ar/llvm-6502.git
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Addition of the PPC32 Pattern ISel. While it is far from complete, it will
be brought up to parity with the current simple ISel in the coming days. Currently, -pattern-isel is required to trigger it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20805 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
85fdeb233e
commit
a9795f81e9
@ -24,6 +24,7 @@ class TargetMachine;
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FunctionPass *createPPCBranchSelectionPass();
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FunctionPass *createPPC32ISelSimple(TargetMachine &TM);
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FunctionPass *createPPC32ISelPattern(TargetMachine &TM);
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FunctionPass *createPPC64ISelSimple(TargetMachine &TM);
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FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM);
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FunctionPass *createAIXAsmPrinter(std::ostream &OS, TargetMachine &TM);
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756
lib/Target/PowerPC/PPCISelPattern.cpp
Normal file
756
lib/Target/PowerPC/PPCISelPattern.cpp
Normal file
@ -0,0 +1,756 @@
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//===-- PPC32ISelPattern.cpp - A pattern matching inst selector for PPC32 -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pattern matching instruction selector for 32 bit PowerPC.
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//
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//===----------------------------------------------------------------------===//
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#include "PowerPC.h"
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#include "PowerPCInstrBuilder.h"
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#include "PowerPCInstrInfo.h"
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#include "PPC32RegisterInfo.h"
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#include "llvm/Constants.h" // FIXME: REMOVE
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include <set>
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#include <algorithm>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// PPC32TargetLowering - PPC32 Implementation of the TargetLowering interface
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namespace {
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class PPC32TargetLowering : public TargetLowering {
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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int ReturnAddrIndex; // FrameIndex for return slot.
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public:
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PPC32TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
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// Set up the TargetLowering object.
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// Set up the register classes.
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addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
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addRegisterClass(MVT::f32, PPC32::GPRCRegisterClass);
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addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
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computeRegisterProperties();
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}
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/// LowerArguments - This hook must be implemented to indicate how we should
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/// lower the arguments for the specified function, into the specified DAG.
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virtual std::vector<SDOperand>
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LowerArguments(Function &F, SelectionDAG &DAG);
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/// LowerCallTo - This hook lowers an abstract call to a function into an
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/// actual call.
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virtual std::pair<SDOperand, SDOperand>
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LowerCallTo(SDOperand Chain, const Type *RetTy, SDOperand Callee,
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ArgListTy &Args, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
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virtual std::pair<SDOperand,SDOperand>
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LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
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const Type *ArgTy, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
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SelectionDAG &DAG);
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};
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}
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std::vector<SDOperand>
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PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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//
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// add beautiful description of PPC stack frame format, or at least some docs
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//
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineBasicBlock& BB = MF.front();
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std::vector<SDOperand> ArgValues;
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// Due to the rather complicated nature of the PowerPC ABI, rather than a
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// fixed size array of physical args, for the sake of simplicity let the STL
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// handle tracking them for us.
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std::vector<unsigned> argVR, argPR, argOp;
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unsigned ArgOffset = 24;
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unsigned GPR_remaining = 8;
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unsigned FPR_remaining = 13;
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unsigned GPR_idx = 0, FPR_idx = 0;
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static const unsigned GPR[] = {
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PPC::R3, PPC::R4, PPC::R5, PPC::R6,
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PPC::R7, PPC::R8, PPC::R9, PPC::R10,
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};
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static const unsigned FPR[] = {
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PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
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PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
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};
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// Add DAG nodes to load the arguments... On entry to a function on PPC,
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// the arguments start at offset 24, although they are likely to be passed
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// in registers.
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
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SDOperand newroot, argt;
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unsigned ObjSize;
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bool needsLoad = false;
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MVT::ValueType ObjectVT = getValueType(I->getType());
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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ObjSize = 4;
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if (GPR_remaining > 0) {
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BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
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unsigned virtReg =
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MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32));
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argt = newroot = DAG.getCopyFromReg(virtReg, MVT::i32, DAG.getRoot());
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if (ObjectVT != MVT::i32)
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argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
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argVR.push_back(virtReg);
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argPR.push_back(GPR[GPR_idx]);
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argOp.push_back(PPC::OR);
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} else {
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needsLoad = true;
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}
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break;
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case MVT::i64: ObjSize = 8;
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if (GPR_remaining > 1) {
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BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
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BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx+1]);
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MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32));
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unsigned virtReg =
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MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32))-1;
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// FIXME: is this correct?
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argt = newroot = DAG.getCopyFromReg(virtReg, MVT::i32, DAG.getRoot());
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argt = DAG.getCopyFromReg(virtReg+1, MVT::i32, newroot);
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// Push the arguments for emitting into BB later
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argVR.push_back(virtReg); argVR.push_back(virtReg+1);
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argPR.push_back(GPR[GPR_idx]); argPR.push_back(GPR[GPR_idx+1]);
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argOp.push_back(PPC::OR); argOp.push_back(PPC::OR);
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} else {
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needsLoad = true;
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}
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break;
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case MVT::f32: ObjSize = 4;
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case MVT::f64: ObjSize = 8;
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if (FPR_remaining > 0) {
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BuildMI(&BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
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unsigned virtReg =
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MF.getSSARegMap()->createVirtualRegister(getRegClassFor(ObjectVT));
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argt = newroot = DAG.getCopyFromReg(virtReg, ObjectVT, DAG.getRoot());
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argVR.push_back(virtReg);
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argPR.push_back(FPR[FPR_idx]);
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argOp.push_back(PPC::FMR);
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--FPR_remaining;
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++FPR_idx;
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} else {
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needsLoad = true;
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}
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break;
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}
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// We need to load the argument to a virtual register if we determined above
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// that we ran out of physical registers of the appropriate type
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if (needsLoad) {
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int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
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argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
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}
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// Every 4 bytes of argument space consumes one of the GPRs available for
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// argument passing.
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if (GPR_remaining > 0) {
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unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
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GPR_remaining -= delta;
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GPR_idx += delta;
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}
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ArgOffset += ObjSize;
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DAG.setRoot(newroot.getValue(1));
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ArgValues.push_back(argt);
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}
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for (int i = 0, count = argVR.size(); i < count; ++i) {
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if (argOp[i] == PPC::FMR)
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BuildMI(&BB, argOp[i], 1, argVR[i]).addReg(argPR[i]);
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else
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BuildMI(&BB, argOp[i], 2, argVR[i]).addReg(argPR[i]).addReg(argPR[i]);
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}
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// If the function takes variable number of arguments, make a frame index for
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// the start of the first vararg value... for expansion of llvm.va_start.
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if (F.isVarArg())
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VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
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return ArgValues;
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}
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std::pair<SDOperand, SDOperand>
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PPC32TargetLowering::LowerCallTo(SDOperand Chain,
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const Type *RetTy, SDOperand Callee,
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ArgListTy &Args, SelectionDAG &DAG) {
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// FIXME
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int NumBytes = 56;
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Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
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DAG.getConstant(NumBytes, getPointerTy()));
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std::vector<SDOperand> args_to_use;
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for (unsigned i = 0, e = Args.size(); i != e; ++i)
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{
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switch (getValueType(Args[i].second)) {
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default: assert(0 && "Unexpected ValueType for argument!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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case MVT::f64:
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case MVT::f32:
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break;
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}
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args_to_use.push_back(Args[i].first);
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}
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std::vector<MVT::ValueType> RetVals;
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MVT::ValueType RetTyVT = getValueType(RetTy);
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if (RetTyVT != MVT::isVoid)
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RetVals.push_back(RetTyVT);
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RetVals.push_back(MVT::Other);
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SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
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Chain, Callee, args_to_use), 0);
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Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
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Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
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DAG.getConstant(NumBytes, getPointerTy()));
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return std::make_pair(TheCall, Chain);
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}
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std::pair<SDOperand, SDOperand>
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PPC32TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
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//vastart just returns the address of the VarArgsFrameIndex slot.
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return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32), Chain);
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}
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std::pair<SDOperand,SDOperand> PPC32TargetLowering::
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LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
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const Type *ArgTy, SelectionDAG &DAG) {
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abort();
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}
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std::pair<SDOperand, SDOperand> PPC32TargetLowering::
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LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
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SelectionDAG &DAG) {
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abort();
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}
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namespace {
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//===--------------------------------------------------------------------===//
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/// ISel - PPC32 specific code to select PPC32 machine instructions for
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/// SelectionDAG operations.
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//===--------------------------------------------------------------------===//
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class ISel : public SelectionDAGISel {
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/// Comment Here.
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PPC32TargetLowering PPC32Lowering;
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/// ExprMap - As shared expressions are codegen'd, we keep track of which
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/// vreg the value is produced in, so we only emit one copy of each compiled
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/// tree.
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std::map<SDOperand, unsigned> ExprMap;
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public:
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ISel(TargetMachine &TM) : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM)
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{}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// Codegen the basic block.
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Select(DAG.getRoot());
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// Clear state used for selection.
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ExprMap.clear();
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}
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unsigned SelectExpr(SDOperand N);
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unsigned SelectExprFP(SDOperand N, unsigned Result);
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void Select(SDOperand N);
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void SelectAddr(SDOperand N, unsigned& Reg, int& offset);
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void SelectBranchCC(SDOperand N);
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};
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/// canUseAsImmediateForOpcode - This method returns a value indicating whether
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/// the ConstantSDNode N can be used as an immediate to Opcode. The return
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/// values are either 0, 1 or 2. 0 indicates that either N is not a
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/// ConstantSDNode, or is not suitable for use by that opcode. A return value
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/// of 1 indicates that the constant may be used in normal immediate form. A
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/// return value of 2 indicates that the constant may be used in shifted
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/// immediate form. If the return value is nonzero, the constant value is
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/// placed in Imm.
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///
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static unsigned canUseAsImmediateForOpcode(SDOperand N, unsigned Opcode,
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unsigned& Imm) {
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if (N.getOpcode() != ISD::Constant) return 0;
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int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
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switch(Opcode) {
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default: return 0;
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case ISD::ADD:
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if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
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if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
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break;
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case ISD::AND:
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case ISD::XOR:
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case ISD::OR:
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if (v >= 0 && v <= 65535) { Imm = v & 0xFFFF; return 1; }
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if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
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break;
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}
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return 0;
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}
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}
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//Check to see if the load is a constant offset from a base register
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void ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
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{
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Reg = SelectExpr(N);
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offset = 0;
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return;
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}
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void ISel::SelectBranchCC(SDOperand N)
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{
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assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
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MachineBasicBlock *Dest =
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cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
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unsigned Opc;
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Select(N.getOperand(0)); //chain
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SDOperand CC = N.getOperand(1);
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//Giveup and do the stupid thing
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unsigned Tmp1 = SelectExpr(CC);
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BuildMI(BB, PPC::BNE, 2).addReg(Tmp1).addMBB(Dest);
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return;
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}
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unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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{
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unsigned Tmp1, Tmp2, Tmp3;
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unsigned Opc = 0;
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SDNode *Node = N.Val;
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MVT::ValueType DestType = N.getValueType();
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unsigned opcode = N.getOpcode();
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switch (opcode) {
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default:
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Node->dump();
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assert(0 && "Node not handled!\n");
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case ISD::SELECT:
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abort();
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case ISD::FP_ROUND:
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assert (DestType == MVT::f32 &&
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N.getOperand(0).getValueType() == MVT::f64 &&
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"only f64 to f32 conversion supported here");
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
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return Result;
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case ISD::FP_EXTEND:
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assert (DestType == MVT::f64 &&
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N.getOperand(0).getValueType() == MVT::f32 &&
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"only f32 to f64 conversion supported here");
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
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return Result;
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case ISD::CopyFromReg:
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// FIXME: Handle copy from physregs!
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// Just use the specified register as our input.
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return dyn_cast<RegSDNode>(Node)->getReg();
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case ISD::LOAD:
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abort();
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case ISD::ConstantFP:
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abort();
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case ISD::MUL:
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case ISD::ADD:
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case ISD::SUB:
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case ISD::SDIV:
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switch( opcode ) {
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case ISD::MUL: Opc = DestType == MVT::f64 ? PPC::FMUL : PPC::FMULS; break;
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case ISD::ADD: Opc = DestType == MVT::f64 ? PPC::FADD : PPC::FADDS; break;
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case ISD::SUB: Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS; break;
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case ISD::SDIV: Opc = DestType == MVT::f64 ? PPC::FDIV : PPC::FDIVS; break;
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};
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|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
Tmp2 = SelectExpr(N.getOperand(1));
|
||||
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
||||
return Result;
|
||||
|
||||
case ISD::EXTLOAD:
|
||||
abort();
|
||||
|
||||
case ISD::UINT_TO_FP:
|
||||
case ISD::SINT_TO_FP:
|
||||
abort();
|
||||
}
|
||||
assert(0 && "should not get here");
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned ISel::SelectExpr(SDOperand N) {
|
||||
unsigned Result;
|
||||
unsigned Tmp1, Tmp2, Tmp3;
|
||||
unsigned Opc = 0;
|
||||
unsigned opcode = N.getOpcode();
|
||||
|
||||
SDNode *Node = N.Val;
|
||||
MVT::ValueType DestType = N.getValueType();
|
||||
|
||||
unsigned &Reg = ExprMap[N];
|
||||
if (Reg) return Reg;
|
||||
|
||||
if (DestType == MVT::f64 || DestType == MVT::f32)
|
||||
return SelectExprFP(N, Result);
|
||||
|
||||
if (N.getOpcode() != ISD::CALL)
|
||||
Reg = Result = (N.getValueType() != MVT::Other) ?
|
||||
MakeReg(N.getValueType()) : 1;
|
||||
else
|
||||
abort(); // FIXME: Implement Call
|
||||
|
||||
switch (opcode) {
|
||||
default:
|
||||
Node->dump();
|
||||
assert(0 && "Node not handled!\n");
|
||||
|
||||
case ISD::DYNAMIC_STACKALLOC:
|
||||
abort();
|
||||
|
||||
case ISD::ConstantPool:
|
||||
abort();
|
||||
|
||||
case ISD::FrameIndex:
|
||||
abort();
|
||||
|
||||
case ISD::EXTLOAD:
|
||||
case ISD::ZEXTLOAD:
|
||||
case ISD::SEXTLOAD:
|
||||
case ISD::LOAD:
|
||||
case ISD::GlobalAddress:
|
||||
case ISD::CALL:
|
||||
abort();
|
||||
|
||||
case ISD::SIGN_EXTEND:
|
||||
case ISD::SIGN_EXTEND_INREG:
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
|
||||
return Result;
|
||||
|
||||
case ISD::ZERO_EXTEND_INREG:
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
|
||||
default:
|
||||
Node->dump();
|
||||
assert(0 && "Zero Extend InReg not there yet");
|
||||
break;
|
||||
case MVT::i16: Tmp2 = 16; break;
|
||||
case MVT::i8: Tmp2 = 24; break;
|
||||
case MVT::i1: Tmp2 = 31; break;
|
||||
}
|
||||
BuildMI(BB, PPC::RLWINM, 5, Result).addReg(Tmp1).addImm(0).addImm(0)
|
||||
.addImm(Tmp2).addImm(31);
|
||||
return Result;
|
||||
|
||||
case ISD::SETCC:
|
||||
abort();
|
||||
|
||||
case ISD::CopyFromReg:
|
||||
if (Result == 1)
|
||||
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
|
||||
Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
|
||||
BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
|
||||
return Result;
|
||||
|
||||
case ISD::SHL:
|
||||
case ISD::SRL:
|
||||
case ISD::SRA:
|
||||
case ISD::MUL:
|
||||
abort();
|
||||
|
||||
case ISD::ADD:
|
||||
assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
switch(canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
|
||||
default: assert(0 && "unhandled result code");
|
||||
case 0: // No immediate
|
||||
Tmp2 = SelectExpr(N.getOperand(1));
|
||||
BuildMI(BB, PPC::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
||||
break;
|
||||
case 1: // Low immediate
|
||||
BuildMI(BB, PPC::ADDI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
|
||||
break;
|
||||
case 2: // Shifted immediate
|
||||
BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Tmp1).addSImm(Tmp2);
|
||||
break;
|
||||
}
|
||||
return Result;
|
||||
|
||||
case ISD::SUB:
|
||||
abort();
|
||||
|
||||
case ISD::AND:
|
||||
case ISD::OR:
|
||||
case ISD::XOR:
|
||||
assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
switch(canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
|
||||
default: assert(0 && "unhandled result code");
|
||||
case 0: // No immediate
|
||||
Tmp2 = SelectExpr(N.getOperand(1));
|
||||
switch (opcode) {
|
||||
case ISD::AND: Tmp3 = PPC::AND; break;
|
||||
case ISD::OR: Tmp3 = PPC::OR; break;
|
||||
case ISD::XOR: Tmp3 = PPC::XOR; break;
|
||||
}
|
||||
BuildMI(BB, Tmp3, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
||||
break;
|
||||
case 1: // Low immediate
|
||||
switch (opcode) {
|
||||
case ISD::AND: Tmp3 = PPC::ANDIo; break;
|
||||
case ISD::OR: Tmp3 = PPC::ORI; break;
|
||||
case ISD::XOR: Tmp3 = PPC::XORI; break;
|
||||
}
|
||||
BuildMI(BB, Tmp3, 2, Result).addReg(Tmp1).addImm(Tmp2);
|
||||
break;
|
||||
case 2: // Shifted immediate
|
||||
switch (opcode) {
|
||||
case ISD::AND: Tmp3 = PPC::ANDISo; break;
|
||||
case ISD::OR: Tmp3 = PPC::ORIS; break;
|
||||
case ISD::XOR: Tmp3 = PPC::XORIS; break;
|
||||
}
|
||||
BuildMI(BB, Tmp3, 2, Result).addReg(Tmp1).addImm(Tmp2);
|
||||
break;
|
||||
}
|
||||
return Result;
|
||||
|
||||
case ISD::UREM:
|
||||
case ISD::SREM:
|
||||
case ISD::SDIV:
|
||||
case ISD::UDIV:
|
||||
abort();
|
||||
|
||||
case ISD::FP_TO_UINT:
|
||||
case ISD::FP_TO_SINT:
|
||||
abort();
|
||||
|
||||
case ISD::SELECT:
|
||||
abort();
|
||||
|
||||
case ISD::Constant:
|
||||
switch (N.getValueType()) {
|
||||
default: assert(0 && "Cannot use constants of this type!");
|
||||
case MVT::i1:
|
||||
BuildMI(BB, PPC::LI, 1, Result)
|
||||
.addSImm(!cast<ConstantSDNode>(N)->isNullValue());
|
||||
break;
|
||||
case MVT::i32:
|
||||
{
|
||||
int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
|
||||
if (v < 32768 && v >= -32768) {
|
||||
BuildMI(BB, PPC::LI, 1, Result).addSImm(v);
|
||||
} else {
|
||||
unsigned Temp = MakeReg(MVT::i32);
|
||||
BuildMI(BB, PPC::LIS, 1, Temp).addSImm(v >> 16);
|
||||
BuildMI(BB, PPC::ORI, 2, Result).addReg(Temp).addImm(v & 0xFFFF);
|
||||
}
|
||||
}
|
||||
}
|
||||
return Result;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ISel::Select(SDOperand N) {
|
||||
unsigned Tmp1, Tmp2, Opc;
|
||||
unsigned opcode = N.getOpcode();
|
||||
|
||||
if (!ExprMap.insert(std::make_pair(N, 1)).second)
|
||||
return; // Already selected.
|
||||
|
||||
SDNode *Node = N.Val;
|
||||
|
||||
switch (Node->getOpcode()) {
|
||||
default:
|
||||
Node->dump(); std::cerr << "\n";
|
||||
assert(0 && "Node not handled yet!");
|
||||
case ISD::EntryToken: return; // Noop
|
||||
case ISD::TokenFactor:
|
||||
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
|
||||
Select(Node->getOperand(i));
|
||||
return;
|
||||
case ISD::ADJCALLSTACKDOWN:
|
||||
case ISD::ADJCALLSTACKUP:
|
||||
Select(N.getOperand(0));
|
||||
Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
|
||||
Opc = N.getOpcode() == ISD::ADJCALLSTACKDOWN ? PPC::ADJCALLSTACKDOWN :
|
||||
PPC::ADJCALLSTACKUP;
|
||||
BuildMI(BB, Opc, 1).addImm(Tmp1);
|
||||
return;
|
||||
case ISD::BR: {
|
||||
MachineBasicBlock *Dest =
|
||||
cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
|
||||
|
||||
Select(N.getOperand(0));
|
||||
BuildMI(BB, PPC::B, 1).addMBB(Dest);
|
||||
return;
|
||||
}
|
||||
case ISD::BRCOND:
|
||||
SelectBranchCC(N);
|
||||
return;
|
||||
case ISD::CopyToReg:
|
||||
Select(N.getOperand(0));
|
||||
Tmp1 = SelectExpr(N.getOperand(1));
|
||||
Tmp2 = cast<RegSDNode>(N)->getReg();
|
||||
|
||||
if (Tmp1 != Tmp2) {
|
||||
if (N.getOperand(1).getValueType() == MVT::f64 ||
|
||||
N.getOperand(1).getValueType() == MVT::f32)
|
||||
BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
|
||||
else
|
||||
BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
|
||||
}
|
||||
return;
|
||||
case ISD::ImplicitDef:
|
||||
Select(N.getOperand(0));
|
||||
BuildMI(BB, PPC::IMPLICIT_DEF, 0, cast<RegSDNode>(N)->getReg());
|
||||
return;
|
||||
case ISD::RET:
|
||||
switch (N.getNumOperands()) {
|
||||
default:
|
||||
assert(0 && "Unknown return instruction!");
|
||||
case 3:
|
||||
assert(N.getOperand(1).getValueType() == MVT::i32 &&
|
||||
N.getOperand(2).getValueType() == MVT::i32 &&
|
||||
"Unknown two-register value!");
|
||||
Select(N.getOperand(0));
|
||||
Tmp1 = SelectExpr(N.getOperand(1));
|
||||
Tmp2 = SelectExpr(N.getOperand(2));
|
||||
BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
|
||||
BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(Tmp2).addReg(Tmp2);
|
||||
break;
|
||||
case 2:
|
||||
Select(N.getOperand(0));
|
||||
Tmp1 = SelectExpr(N.getOperand(1));
|
||||
switch (N.getOperand(1).getValueType()) {
|
||||
default:
|
||||
assert(0 && "Unknown return type!");
|
||||
case MVT::f64:
|
||||
case MVT::f32:
|
||||
BuildMI(BB, PPC::FMR, 1, PPC::F1).addReg(Tmp1);
|
||||
break;
|
||||
case MVT::i32:
|
||||
BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
|
||||
return;
|
||||
|
||||
case ISD::TRUNCSTORE:
|
||||
case ISD::STORE:
|
||||
{
|
||||
SDOperand Chain = N.getOperand(0);
|
||||
SDOperand Value = N.getOperand(1);
|
||||
SDOperand Address = N.getOperand(2);
|
||||
Select(Chain);
|
||||
|
||||
Tmp1 = SelectExpr(Value); //value
|
||||
|
||||
if (opcode == ISD::STORE) {
|
||||
switch(Value.getValueType()) {
|
||||
default: assert(0 && "unknown Type in store");
|
||||
case MVT::i32: Opc = PPC::STW; break;
|
||||
case MVT::f64: Opc = PPC::STFD; break;
|
||||
case MVT::f32: Opc = PPC::STFS; break;
|
||||
}
|
||||
} else { //ISD::TRUNCSTORE
|
||||
switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
|
||||
default: assert(0 && "unknown Type in store");
|
||||
case MVT::i1: //FIXME: DAG does not promote this load
|
||||
case MVT::i8: Opc = PPC::STB; break;
|
||||
case MVT::i16: Opc = PPC::STH; break;
|
||||
}
|
||||
}
|
||||
|
||||
if (Address.getOpcode() == ISD::GlobalAddress)
|
||||
{
|
||||
BuildMI(BB, Opc, 2).addReg(Tmp1)
|
||||
.addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
|
||||
}
|
||||
else if(Address.getOpcode() == ISD::FrameIndex)
|
||||
{
|
||||
BuildMI(BB, Opc, 2).addReg(Tmp1)
|
||||
.addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex());
|
||||
}
|
||||
else
|
||||
{
|
||||
int offset;
|
||||
SelectAddr(Address, Tmp2, offset);
|
||||
BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
|
||||
}
|
||||
return;
|
||||
}
|
||||
case ISD::EXTLOAD:
|
||||
case ISD::SEXTLOAD:
|
||||
case ISD::ZEXTLOAD:
|
||||
case ISD::LOAD:
|
||||
case ISD::CopyFromReg:
|
||||
case ISD::CALL:
|
||||
case ISD::DYNAMIC_STACKALLOC:
|
||||
ExprMap.erase(N);
|
||||
SelectExpr(N);
|
||||
return;
|
||||
}
|
||||
assert(0 && "Should not be reached!");
|
||||
}
|
||||
|
||||
|
||||
/// createPPC32PatternInstructionSelector - This pass converts an LLVM function
|
||||
/// into a machine code representation using pattern matching and a machine
|
||||
/// description file.
|
||||
///
|
||||
FunctionPass *llvm::createPPC32ISelPattern(TargetMachine &TM) {
|
||||
return new ISel(TM);
|
||||
}
|
||||
@ -37,6 +37,8 @@ namespace llvm {
|
||||
cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc",
|
||||
cl::desc("Enable LSR for PPC (beta option!)"),
|
||||
cl::Hidden);
|
||||
cl::opt<bool> EnablePatternISel("pattern-isel", cl::Hidden,
|
||||
cl::desc("Enable the pattern isel XXX FIXME"));
|
||||
}
|
||||
|
||||
namespace {
|
||||
@ -96,6 +98,8 @@ bool PowerPCTargetMachine::addPassesToEmitAssembly(PassManager &PM,
|
||||
|
||||
if (LP64)
|
||||
PM.add(createPPC64ISelSimple(*this));
|
||||
else if (EnablePatternISel)
|
||||
PM.add(createPPC32ISelPattern(*this));
|
||||
else
|
||||
PM.add(createPPC32ISelSimple(*this));
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user