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Set Inst{15-12} (Rd/Rt) to 0b1111 (PC) for BR_JTadd, BR_JTr, and BR_JTm to

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distinguish between them and the more generic instructions (add, mov, and ldr).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89108 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2009-11-17 17:17:50 +00:00
parent 56ea69c3a2
commit a9ea9ec194
1 changed files with 3 additions and 0 deletions
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3
lib/Target/ARM/ARMInstrInfo.td
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@ -759,6 +759,7 @@ let isBranch = 1, isTerminator = 1 in {
def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
IIC_Br, "mov\tpc, $target \n$jt", IIC_Br, "mov\tpc, $target \n$jt",
[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> { [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
let Inst{15-12} = 0b1111;
let Inst{20} = 0; // S Bit let Inst{20} = 0; // S Bit
let Inst{24-21} = 0b1101; let Inst{24-21} = 0b1101;
let Inst{27-25} = 0b000; let Inst{27-25} = 0b000;
@ -768,6 +769,7 @@ let isBranch = 1, isTerminator = 1 in {
IIC_Br, "ldr\tpc, $target \n$jt", IIC_Br, "ldr\tpc, $target \n$jt",
[(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
imm:$id)]> { imm:$id)]> {
let Inst{15-12} = 0b1111;
let Inst{20} = 1; // L bit let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit let Inst{22} = 0; // B bit
@ -779,6 +781,7 @@ let isBranch = 1, isTerminator = 1 in {
IIC_Br, "add\tpc, $target, $idx \n$jt", IIC_Br, "add\tpc, $target, $idx \n$jt",
[(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
imm:$id)]> { imm:$id)]> {
let Inst{15-12} = 0b1111;
let Inst{20} = 0; // S bit let Inst{20} = 0; // S bit
let Inst{24-21} = 0b0100; let Inst{24-21} = 0b0100;
let Inst{27-25} = 0b000; let Inst{27-25} = 0b000;