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AVX-512: Fixed extract_vector_elt for v8i1 vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202624 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7697,7 +7697,8 @@ static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
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/// Extract one bit from mask vector, like v16i1 or v8i1.
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/// Extract one bit from mask vector, like v16i1 or v8i1.
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/// AVX-512 feature.
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/// AVX-512 feature.
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static SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) {
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SDValue
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X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
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SDValue Vec = Op.getOperand(0);
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SDValue Vec = Op.getOperand(0);
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SDLoc dl(Vec);
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SDLoc dl(Vec);
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MVT VecVT = Vec.getSimpleValueType();
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MVT VecVT = Vec.getSimpleValueType();
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@ -7717,7 +7718,8 @@ static SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) {
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}
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}
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unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
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unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
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unsigned MaxSift = VecVT.getSizeInBits() - 1;
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const TargetRegisterClass* rc = getRegClassFor(VecVT);
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unsigned MaxSift = rc->getSize()*8 - 1;
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Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
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Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
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DAG.getConstant(MaxSift - IdxVal, MVT::i8));
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DAG.getConstant(MaxSift - IdxVal, MVT::i8));
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Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
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Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
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@ -867,6 +867,7 @@ namespace llvm {
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SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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@ -1213,6 +1213,11 @@ def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
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def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
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def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
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(v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
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(v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
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def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
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(v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
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def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
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(v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// AVX-512 - Aligned and unaligned load and store
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// AVX-512 - Aligned and unaligned load and store
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//
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//
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@ -466,10 +466,10 @@ def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
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// The size of the all masked registers is 16 bit because we have only one
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// The size of the all masked registers is 16 bit because we have only one
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// KMOVW istruction that can store this register in memory, and it writes 2 bytes
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// KMOVW istruction that can store this register in memory, and it writes 2 bytes
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def VK1 : RegisterClass<"X86", [i1], 16, (sequence "K%u", 0, 7)>;
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def VK1 : RegisterClass<"X86", [i1], 16, (sequence "K%u", 0, 7)>;
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def VK8 : RegisterClass<"X86", [v8i1], 16, (sequence "K%u", 0, 7)>;
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def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK1)> {let Size = 16;}
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def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)>;
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def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;}
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def VK1WM : RegisterClass<"X86", [i1], 16, (sub VK1, K0)>;
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def VK1WM : RegisterClass<"X86", [i1], 16, (sub VK1, K0)> {let Size = 16;}
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def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)>;
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def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;}
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def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)>;
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def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)>;
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@ -91,7 +91,7 @@ define float @test9(<8 x float> %x, i32 %ind) nounwind {
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;CHECK-LABEL: test10
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;CHECK-LABEL: test10
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;CHECK: vmovd
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;CHECK: vmovd
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;CHECK: vpermd %zmm
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;CHECK: vpermd %zmm
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;CHEKK: vmovdz %xmm0, %eax
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;CHECK: vmovd %xmm0, %eax
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;CHECK: ret
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;CHECK: ret
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define i32 @test10(<16 x i32> %x, i32 %ind) nounwind {
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define i32 @test10(<16 x i32> %x, i32 %ind) nounwind {
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%e = extractelement <16 x i32> %x, i32 %ind
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%e = extractelement <16 x i32> %x, i32 %ind
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@ -100,8 +100,8 @@ define i32 @test10(<16 x i32> %x, i32 %ind) nounwind {
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;CHECK-LABEL: test11
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;CHECK-LABEL: test11
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;CHECK: vpcmpltud
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;CHECK: vpcmpltud
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;CKECK: kshiftlw $11
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;CHECK: kshiftlw $11
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;CKECK: kshiftrw $15
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;CHECK: kshiftrw $15
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;CHECK: kortestw
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;CHECK: kortestw
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;CHECK: je
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;CHECK: je
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;CHECK: ret
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;CHECK: ret
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@ -119,8 +119,8 @@ define <16 x i32> @test11(<16 x i32>%a, <16 x i32>%b) {
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;CHECK-LABEL: test12
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;CHECK-LABEL: test12
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;CHECK: vpcmpgtq
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;CHECK: vpcmpgtq
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;CKECK: kshiftlw $15
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;CHECK: kshiftlw $15
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;CKECK: kshiftrw $15
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;CHECK: kshiftrw $15
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;CHECK: kortestw
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;CHECK: kortestw
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;CHECK: ret
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;CHECK: ret
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@ -135,7 +135,7 @@ define i64 @test12(<16 x i64>%a, <16 x i64>%b, i64 %a1, i64 %b1) {
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;CHECK-LABEL: test13
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;CHECK-LABEL: test13
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;CHECK: cmpl
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;CHECK: cmpl
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;CHECK: sbbl
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;CHECK: sbbl
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;CKECK: orl $65532
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;CHECK: orl $65532
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;CHECK: ret
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;CHECK: ret
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define i16 @test13(i32 %a, i32 %b) {
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define i16 @test13(i32 %a, i32 %b) {
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%cmp_res = icmp ult i32 %a, %b
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%cmp_res = icmp ult i32 %a, %b
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@ -144,5 +144,17 @@ define i16 @test13(i32 %a, i32 %b) {
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ret i16 %res
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ret i16 %res
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}
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}
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;CHECK-LABEL: test14
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;CHECK: vpcmpgtq
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;CHECK: kshiftlw $11
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;CHECK: kshiftrw $15
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;CHECK: kortestw
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;CHECK: ret
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define i64 @test14(<8 x i64>%a, <8 x i64>%b, i64 %a1, i64 %b1) {
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%cmpvector_func.i = icmp slt <8 x i64> %a, %b
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%extract24vector_func.i = extractelement <8 x i1> %cmpvector_func.i, i32 4
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%res = select i1 %extract24vector_func.i, i64 %a1, i64 %b1
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ret i64 %res
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}
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