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Don't fold indexed loads into TCRETURNmi64.

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We don't have enough GR64_TC registers when calling a varargs function
with 6 arguments. Since %al holds the number of vector registers used,
only %r11 is available as a scratch register.

This means that addressing modes using both base and index registers
can't be folded into TCRETURNmi64.

<rdar://problem/12282281>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163761 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2012-09-13 00:25:00 +00:00
parent 253353c9cf
commit aa0cfea9a4
4 changed files with 74 additions and 2 deletions
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28
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@@ -204,6 +204,9 @@ namespace {
bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
SDValue &Scale, SDValue &Index, SDValue &Disp,
SDValue &Segment);
bool SelectSingleRegAddr(SDNode *Parent, SDValue N, SDValue &Base,
SDValue &Scale, SDValue &Index, SDValue &Disp,
SDValue &Segment);
bool SelectLEAAddr(SDValue N, SDValue &Base,
SDValue &Scale, SDValue &Index, SDValue &Disp,
SDValue &Segment);
@@ -1319,6 +1322,31 @@ bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
return true;
}
/// SelectSingleRegAddr - Like SelectAddr, but reject any address that would
/// require more than one allocatable register.
///
/// This is used for a TCRETURNmi64 instruction when used to tail call a
/// variadic function with 6 arguments: Only %r11 is available from GR64_TC.
/// The other scratch register, %rax, is needed to pass in the number of vector
/// registers used in the variadic arguments.
///
bool X86DAGToDAGISel::SelectSingleRegAddr(SDNode *Parent, SDValue N,
SDValue &Base,
SDValue &Scale, SDValue &Index,
SDValue &Disp, SDValue &Segment) {
if (!SelectAddr(Parent, N, Base, Scale, Index, Disp, Segment))
return false;
// Anything %RIP relative is fine.
if (RegisterSDNode *Reg = dyn_cast<RegisterSDNode>(Base))
if (Reg->getReg() == X86::RIP)
return true;
// Check that the index register is 0.
if (RegisterSDNode *Reg = dyn_cast<RegisterSDNode>(Index))
if (Reg->getReg() == 0)
return true;
return false;
}
/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
/// match a load whose top elements are either undef or zeros. The load flavor
/// is derived from the type of N, which is either v4f32 or v2f64.

8
lib/Target/X86/X86InstrCompiler.td
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@@ -1041,7 +1041,13 @@ def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
(TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
Requires<[In64BitMode]>;
def : Pat<(X86tcret (load addr:$dst), imm:$off),
// When calling a variadic function with 6 arguments, 7 scratch registers are
// needed since %al holds the number of vector registers used. That leaves %r11
// as the only remaining GR64_TC register for the addressing mode.
//
// The single_reg_addr pattern rejects any addressing modes that would need
// more than one register.
def : Pat<(X86tcret (load single_reg_addr:$dst), imm:$off),
(TCRETURNmi64 addr:$dst, imm:$off)>,
Requires<[In64BitMode]>;

4
lib/Target/X86/X86InstrInfo.td
View File

@@ -543,6 +543,10 @@ def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
[tglobaltlsaddr], []>;
// Same as addr, but reject addressing modes requiring more than one register.
def single_reg_addr : ComplexPattern<iPTR, 5, "SelectSingleRegAddr", [],
[SDNPWantParent]>;
//===----------------------------------------------------------------------===//
// X86 Instruction Predicate Definitions.
def HasCMov : Predicate<"Subtarget->hasCMov()">;