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Update SystemZ to use PSW following the way x86 uses EFLAGS. Besides

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eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen
change.

This unfortunately requires SystemZ to switch to the list-burr
scheduler, in order to handle the physreg defs properly, however
that's what LLVM has available at this time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85357 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-10-28 00:55:57 +00:00
parent 04ea6e5150
commit aa123224c4
3 changed files with 36 additions and 30 deletions
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10
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -75,7 +75,13 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
setStackPointerRegisterToSaveRestore(SystemZ::R15D); setStackPointerRegisterToSaveRestore(SystemZ::R15D);
setSchedulingPreference(SchedulingForLatency);
// TODO: It may be better to default to latency-oriented scheduling, however
// LLVM's current latency-oriented scheduler can't handle physreg definitions
// such as SystemZ has with PSW, so set this to the register-pressure
// scheduler, because it can.
setSchedulingPreference(SchedulingForRegPressure);
setBooleanContents(ZeroOrOneBooleanContent); setBooleanContents(ZeroOrOneBooleanContent);
setOperationAction(ISD::BR_JT, MVT::Other, Expand); setOperationAction(ISD::BR_JT, MVT::Other, Expand);
@ -663,7 +669,7 @@ SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
DebugLoc dl = LHS.getDebugLoc(); DebugLoc dl = LHS.getDebugLoc();
return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP), return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
dl, MVT::Flag, LHS, RHS); dl, MVT::i64, LHS, RHS);
} }

6
lib/Target/SystemZ/SystemZInstrFP.td
View File

@ -25,15 +25,15 @@ def fpimmneg0 : PatLeaf<(fpimm), [{
return N->isExactlyValue(-0.0); return N->isExactlyValue(-0.0);
}]>; }]>;
let usesCustomDAGSchedInserter = 1 in { let Uses = [PSW], usesCustomDAGSchedInserter = 1 in {
def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc), def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
"# SelectF32 PSEUDO", "# SelectF32 PSEUDO",
[(set FP32:$dst, [(set FP32:$dst,
(SystemZselect FP32:$src1, FP32:$src2, imm:$cc))]>; (SystemZselect FP32:$src1, FP32:$src2, imm:$cc, PSW))]>;
def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc), def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
"# SelectF64 PSEUDO", "# SelectF64 PSEUDO",
[(set FP64:$dst, [(set FP64:$dst,
(SystemZselect FP64:$src1, FP64:$src2, imm:$cc))]>; (SystemZselect FP64:$src1, FP64:$src2, imm:$cc, PSW))]>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

50
lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -32,12 +32,12 @@ def SDT_SystemZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>; def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
def SDT_SystemZCallSeqEnd : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>; def SDT_SystemZCallSeqEnd : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
def SDT_CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; def SDT_CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
def SDT_BrCond : SDTypeProfile<0, 2, def SDT_BrCond : SDTypeProfile<0, 3,
[SDTCisVT<0, OtherVT>, [SDTCisVT<0, OtherVT>,
SDTCisI8<1>]>; SDTCisI8<1>, SDTCisVT<2, i64>]>;
def SDT_SelectCC : SDTypeProfile<1, 3, def SDT_SelectCC : SDTypeProfile<1, 4,
[SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
SDTCisI8<3>]>; SDTCisI8<3>, SDTCisVT<4, i64>]>;
def SDT_Address : SDTypeProfile<1, 1, def SDT_Address : SDTypeProfile<1, 1,
[SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
@ -54,11 +54,11 @@ def SystemZcallseq_start :
def SystemZcallseq_end : def SystemZcallseq_end :
SDNode<"ISD::CALLSEQ_END", SDT_SystemZCallSeqEnd, SDNode<"ISD::CALLSEQ_END", SDT_SystemZCallSeqEnd,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def SystemZcmp : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>; def SystemZcmp : SDNode<"SystemZISD::CMP", SDT_CmpTest>;
def SystemZucmp : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>; def SystemZucmp : SDNode<"SystemZISD::UCMP", SDT_CmpTest>;
def SystemZbrcond : SDNode<"SystemZISD::BRCOND", SDT_BrCond, def SystemZbrcond : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
[SDNPHasChain, SDNPInFlag]>; [SDNPHasChain]>;
def SystemZselect : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>; def SystemZselect : SDNode<"SystemZISD::SELECT", SDT_SelectCC>;
def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>; def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
@ -74,15 +74,15 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
"#ADJCALLSTACKUP", "#ADJCALLSTACKUP",
[(SystemZcallseq_end timm:$amt1, timm:$amt2)]>; [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
let usesCustomDAGSchedInserter = 1 in { let Uses = [PSW], usesCustomDAGSchedInserter = 1 in {
def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc), def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
"# Select32 PSEUDO", "# Select32 PSEUDO",
[(set GR32:$dst, [(set GR32:$dst,
(SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>; (SystemZselect GR32:$src1, GR32:$src2, imm:$cc, PSW))]>;
def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc), def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
"# Select64 PSEUDO", "# Select64 PSEUDO",
[(set GR64:$dst, [(set GR64:$dst,
(SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>; (SystemZselect GR64:$src1, GR64:$src2, imm:$cc, PSW))]>;
} }
@ -106,46 +106,46 @@ let isBranch = 1, isTerminator = 1 in {
let Uses = [PSW] in { let Uses = [PSW] in {
def JO : Pseudo<(outs), (ins brtarget:$dst), def JO : Pseudo<(outs), (ins brtarget:$dst),
"jo\t$dst", "jo\t$dst",
[(SystemZbrcond bb:$dst, SYSTEMZ_COND_O)]>; [(SystemZbrcond bb:$dst, SYSTEMZ_COND_O, PSW)]>;
def JH : Pseudo<(outs), (ins brtarget:$dst), def JH : Pseudo<(outs), (ins brtarget:$dst),
"jh\t$dst", "jh\t$dst",
[(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>; [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H, PSW)]>;
def JNLE: Pseudo<(outs), (ins brtarget:$dst), def JNLE: Pseudo<(outs), (ins brtarget:$dst),
"jnle\t$dst", "jnle\t$dst",
[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLE)]>; [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLE, PSW)]>;
def JL : Pseudo<(outs), (ins brtarget:$dst), def JL : Pseudo<(outs), (ins brtarget:$dst),
"jl\t$dst", "jl\t$dst",
[(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>; [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L, PSW)]>;
def JNHE: Pseudo<(outs), (ins brtarget:$dst), def JNHE: Pseudo<(outs), (ins brtarget:$dst),
"jnhe\t$dst", "jnhe\t$dst",
[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NHE)]>; [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NHE, PSW)]>;
def JLH : Pseudo<(outs), (ins brtarget:$dst), def JLH : Pseudo<(outs), (ins brtarget:$dst),
"jlh\t$dst", "jlh\t$dst",
[(SystemZbrcond bb:$dst, SYSTEMZ_COND_LH)]>; [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LH, PSW)]>;
def JNE : Pseudo<(outs), (ins brtarget:$dst), def JNE : Pseudo<(outs), (ins brtarget:$dst),
"jne\t$dst", "jne\t$dst",
[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>; [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE, PSW)]>;
def JE : Pseudo<(outs), (ins brtarget:$dst), def JE : Pseudo<(outs), (ins brtarget:$dst),
"je\t$dst", "je\t$dst",
[(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>; [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E, PSW)]>;
def JNLH: Pseudo<(outs), (ins brtarget:$dst), def JNLH: Pseudo<(outs), (ins brtarget:$dst),
"jnlh\t$dst", "jnlh\t$dst",
[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLH)]>; [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLH, PSW)]>;
def JHE : Pseudo<(outs), (ins brtarget:$dst), def JHE : Pseudo<(outs), (ins brtarget:$dst),
"jhe\t$dst", "jhe\t$dst",
[(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>; [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE, PSW)]>;
def JNL : Pseudo<(outs), (ins brtarget:$dst), def JNL : Pseudo<(outs), (ins brtarget:$dst),
"jnl\t$dst", "jnl\t$dst",
[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NL)]>; [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NL, PSW)]>;
def JLE : Pseudo<(outs), (ins brtarget:$dst), def JLE : Pseudo<(outs), (ins brtarget:$dst),
"jle\t$dst", "jle\t$dst",
[(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>; [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE, PSW)]>;
def JNH : Pseudo<(outs), (ins brtarget:$dst), def JNH : Pseudo<(outs), (ins brtarget:$dst),
"jnh\t$dst", "jnh\t$dst",
[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NH)]>; [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NH, PSW)]>;
def JNO : Pseudo<(outs), (ins brtarget:$dst), def JNO : Pseudo<(outs), (ins brtarget:$dst),
"jno\t$dst", "jno\t$dst",
[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NO)]>; [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NO, PSW)]>;
} // Uses = [PSW] } // Uses = [PSW]
} // isBranch = 1 } // isBranch = 1