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[mips][msa] Added test cases that were supposed to be part of r190507, r190509, r190512, and r190518.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190522 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
160
test/CodeGen/Mips/msa/arithmetic_float.ll
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160
test/CodeGen/Mips/msa/arithmetic_float.ll
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; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
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define void @add_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
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; CHECK: add_v4f32:
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%1 = load <4 x float>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x float>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = fadd <4 x float> %1, %2
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; CHECK-DAG: fadd.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <4 x float> %3, <4 x float>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size add_v4f32
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}
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define void @add_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
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; CHECK: add_v2f64:
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%1 = load <2 x double>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x double>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = fadd <2 x double> %1, %2
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; CHECK-DAG: fadd.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <2 x double> %3, <2 x double>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size add_v2f64
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}
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define void @sub_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
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; CHECK: sub_v4f32:
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%1 = load <4 x float>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x float>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = fsub <4 x float> %1, %2
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; CHECK-DAG: fsub.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <4 x float> %3, <4 x float>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size sub_v4f32
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}
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define void @sub_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
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; CHECK: sub_v2f64:
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%1 = load <2 x double>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x double>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = fsub <2 x double> %1, %2
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; CHECK-DAG: fsub.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <2 x double> %3, <2 x double>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size sub_v2f64
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}
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define void @mul_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
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; CHECK: mul_v4f32:
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%1 = load <4 x float>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x float>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = fmul <4 x float> %1, %2
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; CHECK-DAG: fmul.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <4 x float> %3, <4 x float>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size mul_v4f32
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}
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define void @mul_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
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; CHECK: mul_v2f64:
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%1 = load <2 x double>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x double>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = fmul <2 x double> %1, %2
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; CHECK-DAG: fmul.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <2 x double> %3, <2 x double>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size mul_v2f64
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}
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define void @fdiv_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
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; CHECK: fdiv_v4f32:
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%1 = load <4 x float>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x float>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = fdiv <4 x float> %1, %2
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; CHECK-DAG: fdiv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <4 x float> %3, <4 x float>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size fdiv_v4f32
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}
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define void @fdiv_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
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; CHECK: fdiv_v2f64:
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%1 = load <2 x double>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x double>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = fdiv <2 x double> %1, %2
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; CHECK-DAG: fdiv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <2 x double> %3, <2 x double>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size fdiv_v2f64
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}
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define void @fsqrt_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
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; CHECK: fsqrt_v4f32:
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%1 = load <4 x float>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = tail call <4 x float> @llvm.sqrt.v4f32 (<4 x float> %1)
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; CHECK-DAG: fsqrt.w [[R3:\$w[0-9]+]], [[R1]]
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store <4 x float> %2, <4 x float>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size fsqrt_v4f32
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}
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define void @fsqrt_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
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; CHECK: fsqrt_v2f64:
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%1 = load <2 x double>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = tail call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %1)
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; CHECK-DAG: fsqrt.d [[R3:\$w[0-9]+]], [[R1]]
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store <2 x double> %2, <2 x double>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size fsqrt_v2f64
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}
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declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %Val)
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declare <2 x double> @llvm.sqrt.v2f64(<2 x double> %Val)
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