6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-03 14:31:10 +00:00
Code Issues Projects Releases Wiki Activity

Merging r197572:

Browse Source 
------------------------------------------------------------------------
r197572 | rafael.espindola | 2013-12-18 09:35:37 -0500 (Wed, 18 Dec 2013) | 6 lines

One ppc32-darwin, a i64 inside a structure can have 32 bit alignment.

Thanks for Iain Sandoe for testing this with the original gcc.

Clang was already getting this right.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205766 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2014-04-08 14:27:55 +00:00
parent c428c29241
commit aa3637aafb
2 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -48,7 +48,8 @@ static std::string getDataLayoutString(const PPCSubtarget &ST) {
// Note, the alignment values for f64 and i64 on ppc64 in Darwin
// documentation are wrong; these are correct (i.e. "what gcc does").
Ret += "-f64:64:64-i64:64:64";
if (ST.isPPC64() || ST.isSVR4ABI())
Ret += "-f64:64:64-i64:64:64";
// Set support for 128 floats depending on the ABI.
if (ST.isPPC64() && ST.isSVR4ABI()) {

4
test/CodeGen/PowerPC/anon_aggr.ll
View File

@ -119,9 +119,9 @@ unequal:
; CHECK: ld 3, -[[OFFSET1]](1)
; DARWIN32: _func3:
; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 40
; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 36
; DARWIN32: addi r[[REG2:[0-9]+]], r[[REGSP]], 24
; DARWIN32: lwz r[[REG3:[0-9]+]], 48(r[[REGSP]])
; DARWIN32: lwz r[[REG3:[0-9]+]], 44(r[[REGSP]])
; DARWIN32: lwz r[[REG4:[0-9]+]], 32(r[[REGSP]])
; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]