The LLVM target-indendent code generator is designed to support efficient and +
The LLVM target-independent code generator is designed to support efficient and quality code generation for standard register-based microprocessors. Code generation in this model is divided into the following stages:
@@ -296,6 +314,25 @@ target, and whether the target is little- or big-endian.
The TargetLowering class is used by SelectionDAG based instruction +selectors primarily to describe how LLVM code should be lowered to SelectionDAG +operations. Among other things, this class indicates an initial register class +to use for various ValueTypes, which operations are natively supported by the +target machine, and some other miscellaneous properties (such as the return type +of setcc operations, the type to use for shift amounts, etc).
+ +The opcode number is an simple unsigned number that only has meaning to a specific backend. All of the instructions for a target should be defined in the *InstrInfo.td file for the target, and the opcode enum values -are autogenerated from this description. The MachineInstr class does -not have any information about how to intepret the instruction (i.e., what the +are auto-generated from this description. The MachineInstr class does +not have any information about how to interpret the instruction (i.e., what the semantics of the instruction are): for that you must refer to the TargetInstrInfo class.
@@ -396,7 +433,7 @@ In addition, a machine operand should be marked as a def or a use of the valueBy convention, the LLVM code generator orders instruction operands so that all register definitions come before the register uses, even on architectures -that are normally printed in other orders. For example, the sparc add +that are normally printed in other orders. For example, the SPARC add instruction: "add %i1, %i2, %i3" adds the "%i1", and "%i2" registers and stores the result into the "%i3" register. In the LLVM code generator, the operands should be stored as "%i3, %i1, %i2": with the destination @@ -503,7 +540,7 @@ and ret (use ret -
By the end of code generation, the register allocator has coallesced +
By the end of code generation, the register allocator has coalesced the registers and deleted the resultant identity moves, producing the following code:
@@ -544,6 +581,286 @@ are no virtual registers left in the code.This section documents the phases described in the high-level design of the code generator. It +explains how they work and some of the rationale behind their design.
+ ++Instruction Selection is the process of translating the LLVM code input to the +code generator into target-specific machine instructions. There are several +well-known ways to do this in the literature. In LLVM there are two main forms: +the old-style 'simple' instruction selector (which effectively peephole selects +each LLVM instruction into a series of machine instructions), and the new +SelectionDAG based instruction selector. +
+ +The 'simple' instruction selectors are tedious to write, require a lot of +boiler plate code, and are difficult to get correct. Additionally, any +optimizations written for a simple instruction selector cannot be used by other +targets. For this reason, LLVM is moving to a new SelectionDAG based +instruction selector, which is described in this section. If you are starting a +new port, we recommend that you write the instruction selector using the +SelectionDAG infrastructure.
+ +In time, most of the target-specific code for instruction selection will be +auto-generated from the target .td files. For now, however, the Select Phase must still be written by hand.
++The SelectionDAG provides an abstraction for representing code in a way that is +amenable to instruction selection using automatic techniques +(e.g. dynamic-programming based optimal pattern matching selectors), as well as +an abstraction that is useful for other phases of code generation (in +particular, instruction scheduling). Additionally, the SelectionDAG provides a +host representation where a large variety of very-low-level (but +target-independent) optimizations may be +performed: ones which require extensive information about the instructions +efficiently supported by the target. +
+ ++The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the +SDNode class. The primary payload of the Node is its operation code +(Opcode) that indicates what the operation the node performs. The various +operation node types are described at the top of the +include/llvm/CodeGen/SelectionDAGNodes.h file. Depending on the operation, nodes may contain additional information (e.g. the condition code +for a SETCC node) contained in a derived class.
+ +Each node in the graph may define multiple values +(e.g. for a combined div/rem operation and many other situations), though most +operations define a single value. Each node also has some number of operands, +which are edges to the node defining the used value. Because nodes may define +multiple values, edges are represented by instances of the SDOperand +class, which is a <SDNode, unsigned> pair, indicating the node and result +value being used. Each value produced by a SDNode has an associated +MVT::ValueType, indicating what type the value is. +
+ ++SelectionDAGs contain two different kinds of value: those that represent data +flow and those that represent control flow dependencies. Data values are simple +edges with a integer or floating point value type. Control edges are +represented as "chain" edges which are of type MVT::Other. These edges provide +an ordering between nodes that have side effects (such as +loads/stores/calls/return/etc). All nodes that have side effects should take a +token chain as input and produce a new one as output. By convention, token +chain inputs are always operand #0, and chain results are always the last +value produced by an operation.
+ ++A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is +always a marker node with Opcode of ISD::TokenFactor. The Root node is the +final side effecting node in the token chain (for example, in a single basic +block function, this would be the return node). +
+ ++One important concept for SelectionDAGs is the notion of a "legal" vs "illegal" +DAG. A legal DAG for a target is one that only uses supported operations and +supported types. On PowerPC, for example, a DAG with any values of i1, i8, i16, +or i64 type would be illegal. The legalize +phase is the one responsible for turning an illegal DAG into a legal DAG. +
++SelectionDAG-based instruction selection consists of the following steps: +
+ +After all of these steps are complete, the SelectionDAG is destroyed and the +rest of the code generation passes are run.
+ ++The initial SelectionDAG is naively peephole expanded from the LLVM input by +the SelectionDAGLowering class in the SelectionDAGISel.cpp file. The idea of +doing this pass is to expose as much low-level target-specific details to the +SelectionDAG as possible. This pass is mostly hard-coded (e.g. an LLVM add +turns into a SDNode add, a geteelementptr is expanded into the obvious +arithmetic, etc) but does require target-specific hooks to lower calls and +returns, varargs, etc. For these features, the TargetLowering interface is +used. +
+ +The Legalize phase is in charge of converting a DAG to only use the types and +operations that are natively supported by the target. This involves two major +tasks:
+ +Convert values of unsupported types to values of supported types.
+There are two main ways of doing this: promoting a small type to a larger + type (e.g. f32 -> f64, or i16 -> i32), and expanding larger integer types + to smaller ones (e.g. implementing i64 with i32 operations where + possible). Promotion insert sign and zero extensions as needed to make + sure that the final code has the same behavior as the input.
+Eliminate operations that are not supported by the target in a supported + type.
+Targets often have wierd constraints, such as not supporting every + operation on every supported datatype (e.g. X86 does not support byte + conditional moves). Legalize takes care of either open-coding another + sequence of operations to emulate the operation (this is known as + expansion), promoting to a larger type that supports the operation + (promotion), or can use a target-specific hook to implement the + legalization.
++Instead of using a Legalize pass, we could require that every target-specific +selector support and expand every operator +and type even if they are not supported and may require many instructions to +implement (in fact, this is the approach taken by the "simple" selectors). +However, using a Legalize pass allows all of the cannonicalization patterns to +be shared across targets, and makes it very easy to optimize the cannonicalized +code (because it is still in the form of a DAG). +
+ ++The SelectionDAG optimization phase is run twice for code generation: once +immediately after the DAG is built and once after legalization. The first pass +allows the initial code to be cleaned up, (for example) performing optimizations +that depend on knowing that the operators have restricted type inputs. The second +pass cleans up the messy code generated by the Legalize pass, allowing Legalize to +be very simple (not having to take into account many special cases. +
+ ++One important class of optimizations that this pass will do in the future is +optimizing inserted sign and zero extension instructions. Here are some good +papers on the subject:
+ +
+"Widening
+integer arithmetic"
+Kevin Redwine and Norman Ramsey
+International Conference on Compiler Construction (CC) 2004
+
+ "Effective
+ sign extension elimination"
+ Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani
+ Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
+ and Implementation.
+
The Select phase is the bulk of the target-specific code for instruction +selection. This phase takes a legal SelectionDAG as input, and does simple +pattern matching on the DAG to generate code. In time, the Select phase will +be automatically generated from the targets InstrInfo.td file, which is why we +want to make the Select phase a simple and mechanical as possible.
+ +