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Revert r97064. Duncan pointed out that bitcasts are defined in

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terms of store and load, which means bitcasting between scalar
integer and vector has endian-specific results, which undermines
this whole approach.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97137 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2010-02-25 15:20:39 +00:00
parent 9a49f1552d
commit aa9d854b33
6 changed files with 20 additions and 106 deletions
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9
include/llvm/Target/TargetData.h
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@ -193,7 +193,9 @@ public:
/// getTypeStoreSize - Return the maximum number of bytes that may be
/// overwritten by storing the specified type. For example, returns 5
/// for i36 and 10 for x86_fp80.
uint64_t getTypeStoreSize(const Type *Ty) const;
uint64_t getTypeStoreSize(const Type *Ty) const {
return (getTypeSizeInBits(Ty)+7)/8;
}
/// getTypeStoreSizeInBits - Return the maximum number of bits that may be
/// overwritten by storing the specified type; always a multiple of 8. For
@ -206,7 +208,10 @@ public:
/// of the specified type, including alignment padding. This is the amount
/// that alloca reserves for this type. For example, returns 12 or 16 for
/// x86_fp80, depending on alignment.
uint64_t getTypeAllocSize(const Type* Ty) const;
uint64_t getTypeAllocSize(const Type* Ty) const {
// Round up to the next alignment boundary.
return RoundUpAlignment(getTypeStoreSize(Ty), getABITypeAlignment(Ty));
}
/// getTypeAllocSizeInBits - Return the offset in bits between successive
/// objects of the specified type, including alignment padding; always a

11
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -660,8 +660,7 @@ PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
// Add the offset to the index.
unsigned EltSize = TLI.getTargetData()->
getTypeAllocSize(EltVT.getTypeForEVT(*DAG.getContext()));
unsigned EltSize = EltVT.getSizeInBits()/8;
Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
// Store the scalar value.
@ -1513,9 +1512,8 @@ SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
false, false, 0);
// Add the offset to the index.
unsigned EltSize = TLI.getTargetData()->getTypeAllocSize(
Vec.getValueType().getVectorElementType().getTypeForEVT(*DAG.getContext()));
unsigned EltSize =
Vec.getValueType().getVectorElementType().getSizeInBits()/8;
Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
DAG.getConstant(EltSize, Idx.getValueType()));
@ -1550,8 +1548,7 @@ SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
// Emit a store of each element to the stack slot.
SmallVector<SDValue, 8> Stores;
unsigned TypeByteSize = TLI.getTargetData()->
getTypeAllocSize(EltVT.getTypeForEVT(*DAG.getContext()));
unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
// Store (in the right endianness) the elements to memory.
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
// Ignore undef elements.

3
lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
View File

@ -966,8 +966,7 @@ SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, EVT EltVT,
Index = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Index);
// Calculate the element offset and add it to the pointer.
unsigned EltSize = TLI.getTargetData()->
getTypeAllocSize(EltVT.getTypeForEVT(*DAG.getContext()));
unsigned EltSize = EltVT.getSizeInBits() / 8; // FIXME: should be ABI size.
Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
DAG.getConstant(EltSize, Index.getValueType()));

21
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -715,8 +715,7 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
false, false, 0);
// Increment the pointer to the other part.
unsigned IncrementSize = TLI.getTargetData()->
getTypeAllocSize(Lo.getValueType().getTypeForEVT(*DAG.getContext()));
unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
DAG.getIntPtrConstant(IncrementSize));
@ -758,8 +757,7 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, LoVT, Ch, Ptr, Offset,
SV, SVOffset, LoMemVT, isVolatile, isNonTemporal, Alignment);
unsigned IncrementSize = TLI.getTargetData()->
getTypeAllocSize(LoMemVT.getTypeForEVT(*DAG.getContext()));
unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize));
SVOffset += IncrementSize;
@ -1123,8 +1121,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
EVT LoMemVT, HiMemVT;
GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
unsigned IncrementSize = TLI.getTargetData()->
getTypeAllocSize(LoMemVT.getTypeForEVT(*DAG.getContext()));
unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
if (isTruncating)
Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
@ -2185,8 +2182,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain,
unsigned Offset = 0;
while (LdWidth > 0) {
unsigned Increment = TLI.getTargetData()->
getTypeAllocSize(NewVT.getTypeForEVT(*DAG.getContext()));
unsigned Increment = NewVTWidth / 8;
Offset += Increment;
BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
DAG.getIntPtrConstant(Increment));
@ -2283,8 +2279,7 @@ DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain,
// Load each element and widen
unsigned WidenNumElts = WidenVT.getVectorNumElements();
SmallVector<SDValue, 16> Ops(WidenNumElts);
unsigned Increment = TLI.getTargetData()->
getTypeAllocSize(LdEltVT.getTypeForEVT(*DAG.getContext()));
unsigned Increment = LdEltVT.getSizeInBits() / 8;
Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, SV, SVOffset,
LdEltVT, isVolatile, isNonTemporal, Align);
LdChain.push_back(Ops[0].getValue(1));
@ -2336,8 +2331,7 @@ void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
// Find the largest vector type we can store with
EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
unsigned NewVTWidth = NewVT.getSizeInBits();
unsigned Increment = TLI.getTargetData()->
getTypeAllocSize(NewVT.getTypeForEVT(*DAG.getContext()));
unsigned Increment = NewVTWidth / 8;
if (NewVT.isVector()) {
unsigned NumVTElts = NewVT.getVectorNumElements();
do {
@ -2405,8 +2399,7 @@ DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain,
// the store.
EVT StEltVT = StVT.getVectorElementType();
EVT ValEltVT = ValVT.getVectorElementType();
unsigned Increment = TLI.getTargetData()->
getTypeAllocSize(ValEltVT.getTypeForEVT(*DAG.getContext()));
unsigned Increment = ValEltVT.getSizeInBits() / 8;
unsigned NumElts = StVT.getVectorNumElements();
SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
DAG.getIntPtrConstant(0));

43
lib/Target/TargetData.cpp
View File

@ -455,7 +455,7 @@ uint64_t TargetData::getTypeSizeInBits(const Type *Ty) const {
return getPointerSizeInBits();
case Type::ArrayTyID: {
const ArrayType *ATy = cast<ArrayType>(Ty);
return getTypeSizeInBits(ATy->getElementType())*ATy->getNumElements();
return getTypeAllocSizeInBits(ATy->getElementType())*ATy->getNumElements();
}
case Type::StructTyID:
// Get the layout annotation... which is lazily created on demand.
@ -484,47 +484,6 @@ uint64_t TargetData::getTypeSizeInBits(const Type *Ty) const {
return 0;
}
/// getTypeStoreSize - Return the maximum number of bytes that may be
/// overwritten by storing the specified type. For example, returns 5
/// for i36 and 10 for x86_fp80.
uint64_t TargetData::getTypeStoreSize(const Type *Ty) const {
// Arrays and vectors are allocated as sequences of elements.
if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
if (ATy->getNumElements() == 0)
return 0;
const Type *ElementType = ATy->getElementType();
return getTypeAllocSize(ElementType) * (ATy->getNumElements() - 1) +
getTypeStoreSize(ElementType);
}
if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
const Type *ElementType = VTy->getElementType();
return getTypeAllocSize(ElementType) * (VTy->getNumElements() - 1) +
getTypeStoreSize(ElementType);
}
return (getTypeSizeInBits(Ty)+7)/8;
}
/// getTypeAllocSize - Return the offset in bytes between successive objects
/// of the specified type, including alignment padding. This is the amount
/// that alloca reserves for this type. For example, returns 12 or 16 for
/// x86_fp80, depending on alignment.
uint64_t TargetData::getTypeAllocSize(const Type* Ty) const {
// Arrays and vectors are allocated as sequences of elements.
// Note that this means that things like vectors-of-i1 are not bit-packed
// in memory (except on a hypothetical bit-addressable machine). If
// someone builds hardware with native vector-of-i1 stores and the idiom
// of bitcasting vectors to integers in order to bitpack them for storage
// isn't sufficient, TargetData may need new "size" concept.
if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty))
return getTypeAllocSize(ATy->getElementType()) * ATy->getNumElements();
if (const VectorType *VTy = dyn_cast<VectorType>(Ty))
return getTypeAllocSize(VTy->getElementType()) * VTy->getNumElements();
// Round up to the next alignment boundary.
return RoundUpAlignment(getTypeStoreSize(Ty), getABITypeAlignment(Ty));
}
/*!
\param abi_or_pref Flag that determines which alignment is returned. true
returns the ABI alignment, false returns the preferred alignment.

39
test/CodeGen/X86/vector-of-i1.ll
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@ -1,39 +0,0 @@
; RUN: llc < %s -march=x86-64 | FileCheck %s
; Vectors of i1 are stored with each element having a
; different address. Since the address unit on x86 is 8 bits,
; that means each i1 value takes 8 bits of storage.
; CHECK: store:
; CHECK: movb $1, 7(%rdi)
; CHECK: movb $1, 6(%rdi)
; CHECK: movb $0, 5(%rdi)
; CHECK: movb $0, 4(%rdi)
; CHECK: movb $1, 3(%rdi)
; CHECK: movb $0, 2(%rdi)
; CHECK: movb $1, 1(%rdi)
; CHECK: movb $0, (%rdi)
define void @store(<8 x i1>* %p) nounwind {
store <8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 0, i1 1, i1 1>, <8 x i1>* %p
ret void
}
; CHECK: variable_extract:
; CHECK: movb 7(%rdi),
; CHECK: movb 6(%rdi),
; CHECK: movb 5(%rdi),
define i32 @variable_extract(<8 x i1>* %p, i32 %n) nounwind {
%t = load <8 x i1>* %p
%s = extractelement <8 x i1> %t, i32 %n
%e = zext i1 %s to i32
ret i32 %e
}
; CHECK: constant_extract:
; CHECK: movzbl 3(%rdi), %eax
define i32 @constant_extract(<8 x i1>* %p, i32 %n) nounwind {
%t = load <8 x i1>* %p
%s = extractelement <8 x i1> %t, i32 3
%e = zext i1 %s to i32
ret i32 %e
}